STM32L4A6xG: Use PB4 (NJTRST) as SPI3_MISO?

[CKugl.1]

I need a clarification about something that I read in

RM0351

Reference manual

STM32L47xxx, STM32L48xxx, STM32L49xxx and STM32L4Axxx

advanced Arm®-based 32-bit MCUs

RM0351 Rev 9

...

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode.

The debug pins are in AF pull-up/pull-down after reset:

• PA15: JTDI in pull-up

• PA14: JTCK/SWCLK in pull-down

• PA13: JTMS/SWDAT in pull-up

• PB4: NJTRST in pull-up

• PB3: JTDO in floating state no pull-up/pull-down

...

48.4.4 Using serial wire and releasing the unused debug pins as GPIOs

To use the serial wire DP to release some GPIOs, the user software must change the GPIO (PA15, PB3 and PB4) configuration mode in the GPIO_MODER register.This releases PA15, PB3 and PB4 which now become available as GPIOs.

When debugging, the host performs the following actions:

• Under system reset, all SWJ pins are assigned (JTAG-DP + SW-DP).

• Under system reset, the debugger host sends the JTAG sequence to switch from the

JTAG-DP to the SW-DP.

• Still under system reset, the debugger sets a breakpoint on vector reset.

• The system reset is released and the Core halts.

• All the debug communications from this point are done using the SW-DP. The other

JTAG pins can then be reassigned as GPIOs by the user software.

...

48.4.2 Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). However, the STM32L47x/L48x/L49x/L4Ax MCUs offer the possibility of disabling some or all of the SWJ-DP ports, and therefore the possibility of releasing the associated pins for general-purpose I/O (GPIO) usage, except for NJTRST that can be left disconnected but cannot be used as general purpose GPIO without loosing [sic] debugger connection. [emphasis mine]

I don't understand that last sentence. We're using 2-wire SW-DP, so we don't need NJTRST itself. Can we use PB4 as SPI3_MISO (does that count as general purpose GPIO?) without losing the ability to debug with SW-DP?

[waclawek.jan]

That's probably an infortunately formulated version of the "Full JTAG configuration without NJTRST pin cannot be used" erratum, see errata to your STM32.

JW

@Imen DAHMEN , can this please be reviewed?

​ 

[CKugl.1]

Ah, I bet that's it!

Thanks.

[Imen.D]

Hello @CKugl.1​ , @Community member​ 

Thank you for having reported the point.

I will check this by the next week and come back to you soon with update.

Regards

Imen

[waclawek.jan]

Thanks, Imen.

Jan

@Imen DAHMEN​ 

[Imen.D]

Hello @CKugl.1​ , @Community member​ ,

After checking the reference and the errata: If only Serial Wire is used, PB4 can be used as a GPIO.

I confirm that the RM is wrong on Table 330 row 2 (should have a ‘X).

Imen

[waclawek.jan]

Hi Imen,

Thanks for the explanation.

OK I see why the extra X in the table, although it may get even more confusing and perhaps granting a footnote to the table; but the real problem is the highlighted text in the original post: it now effectively says, that using PB4 as GPIO results in losing [all] debugger connection, whether it's SWD or JTAG - and that is not the case, is it.

Jan

@Imen DAHMEN​