STM32L476 SPI half duplex receive clock

[Jack Peacock_2]

I configured the SPI2 port for bidirectional (BIDIMODE = 1) and rx (BIDIOE = 0), then enabled the port (SPE = 1). According to the RM the enable should immediately start sending clock pulses out the SCK pin and read data on the MOSI pin, since it is half duplex. As long as the port is enabled data should be clocked in continually until the SPI port is disabled (SPE = 0). I expected the RXFIFO to fill with data. SPI port is in master mode (MSTR = 1)

What I actually see is the BSY bit set, TXE set, but no RXNE and no change the FRLVL= 0, empty. It appears no clock pulse are being sent. The Cube examples all show the same procedure, so I'm not clear on what's missing. I can transmit in half duplex but when I switch the line direction to RX (BIDIOE from 1 to 0) the output clock appears to stop.

This should be the equivalent of RXONLY = 1, except for using MOSI instead of MISO. Even if the peripheral is misconfigured something should be clocked in from the MOSI line into the RXFIFO.

Details from ST appear to be few and well hidden on how to use half duplex SPI. Has anyone gotten this mode to work without using the HAL?

Jack Peacock

[S.Ma]

Well, I was able to get to the same point when SCK becomes continuously sent (with debug register watch), and for me this was not the expected behaviour (wanted to have 4 wire SPI behaviour using only 3 Pins).... and on the scope what you expect happened (STM32L4R5) which was incompatible with my needs. So it works as you intended, and didn't save the source code...

[Jack Peacock_2]

Problem solved, sort of. When I changed the GPIO output type settings for the SPI pins from OD to PP the RX clock started working. Lesson learned: forget all about how SPI worked on F1, F2, F4, etc. it's a new IP block even if some aspects look the same. I hope ST eventually adds that little tidbit of information to the RM section on SPI with the caveat it won't work otherwise.

The problem with GPIO of push-pull is with the half-duplex data line. When SPI is disabled it reverts to a PP output instead of open drain. The peripheral on the SPI bus also has a half duplex MISO pin that tries to drive the same line. ST does mention this in an RM footnote with a warning to add a resistor to limit current. Not the best solution in a low power battery design. Might be okay on a F7 part but not an L4.

Jack Peacock

[waclawek.jan]

> When SPI is disabled it reverts to a PP output instead of open drain.

Are you talking about SPI being disabled by clearing SPI_CR1.SPE?

JW