STM32L476 LPTIM1 counter register

[turboscrew]

Posted on October 06, 2017 at 21:42

I know the counter register read is not very reliable:

Bits 15:0 CNT: Counter value

When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may

return unreliable values. So in this case it is necessary to perform two consecutive read accesses

and verify that the two returned values are identical.

It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read

accesses must be performed and compared. A read access can be considered reliable when the

values of the two consecutive read accesses are equal.

But how many reads is normal?

I tried to find the 'edge' by:

uint32_t read_count()

{

    uint32_t tmp1, tmp2;

    tmp1 = HAL_LPTIM_ReadCounter(&hlptim1); // hlptim1 is a global variable

    while ((tmp2 = HAL_LPTIM_ReadCounter(&hlptim1)) != tmp1) tmp1 = tmp2;

    return tmp1;

}

uint32_t poll_count_change()

{

    uint32_t tmp;

    tmp = read_count();

    while (read_count() == tmp);

    return get_systicks();

}

the worst case seemed to be that the poll_count_change() took about 45ms!

Is that anywhere near normal?

The LPTIM1 was running on LSE and with prescaler 2 and the processor was running @ 48MHz.

#stm32l4 #lptim

[waclawek.jan]

Posted on October 06, 2017 at 22:34

IMO the reason for 'unreliability' is that the read might sample the counter while an input pulse ripples through the stages. In other words, it should be 'unstable' only after the vicinity of the input pulse; duration of the 'ripple' should be less than or comparable to (1/maximum clock) x counter bits. Thus, if the input clock is nowhere near this (which it isn't), and you run system clock at the maximum, the reading should be stable within a dozen of system clocks.

I don't quite understand your method though.

JW

[turboscrew]

Posted on October 07, 2017 at 10:20

The read_count() reads until it gets two same values with adjacent reads, an the poll uses that reading and checks when the value changes. With the formula, you mean bus clock (80 mHz)? 12.5 ns * 16 bits = 200ns?

We have a good oscillator for the HSE, except that it's a bit power hungry, and to save battery, we put the device into stop2 mode and switch off the oscillator for most of the time. The system operates in 1s cycles, and the system clock precision needs to be 'carried' over the sleep time such that the error is less than 10 us. The LSE xtal is good enough. The problem is 'transferring' the time from systick to lptim before sleep, and from lptim back to systick after the sleep.

[waclawek.jan]

Posted on October 07, 2017 at 12:29

Please note, that I am not ST.

you mean bus clock (80 mHz)? 12.5 ns * 16 bits = 200ns?

(Please use capital M for Mega prefix)

I mean maximum input frequency to LPTIM's counter input, not the bus clock.

Unfortunately, ST does not specify this; even techsupport could not tell this last time I asked (I was just curious and was not that interested to push this any further). It may be the same as other timers' value (i.e. 80MHz as you've sayd), but it also may be lower, if they used longer transistors in the counter to lower power consumption. But even then I would be surprised if it would be slower than 2-3x the 80MHz rate.

In other words, if you are confident you are reading the LPTIM way faster than it is clocked, then IMO, you should have a stable reading within say 1us. I can't explain your findings and you probably should contact ST through FAE or the support form on web to get further explanation or help.

JW

[turboscrew]

Posted on October 07, 2017 at 12:34

(Please use capital M for Mega prefix)

Oops, typo...

[turboscrew]

Posted on October 07, 2017 at 12:33

I guess it's at least 80 MHz, because the LPTIM can use APB clock as a clock source...

And I guess the same applies to all low power peripherals clocked by a low power side clock (LSE/HSE) - including RTC?

Also, what are the two LPTIM_CFGR fields COUNTMODE and CKSEL?

The explanations in the reference manual look confusing.

Bit 23 COUNTMODE: counter mode enabled

The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:

0: the counter is incremented following each internal clock pulse

1: the counter is incremented following each valid clock pulse on the LPTIM external Input1

Bit 0 CKSEL: Clock selector

The CKSEL bit selects which clock source the LPTIM will use:

0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

1: LPTIM is clocked by an external clock source through the LPTIM external Input1

[waclawek.jan]

Posted on October 07, 2017 at 12:50

Also, what are the two LPTIM_CFGR fields COUNTMODE and CKSEL?

34.4.10  Counter mode deals with them further, but as I've said I am not using the LPTIM at the moment so am not going to dig deeper.

JW

[henry.dick]

Posted on February 14, 2018 at 18:38

How many times to read? As many as necessary. It is essentially asking you to do a double read.

Something like this will work:

  Do (

    Tmp = lptim' cnt

  While (tmp != Lptim' cnt)

  Return tmp

No need to be fancier than that.

[Balasubramanian vaidhyanathan]

Posted on February 15, 2018 at 15:28

Hi Jan

      Here is a small snippet of my settings.I was trying to generate interrupts every 1msec... The plan is to set the ARR to 1000 and timer tick to 1 microseconds. So I configured the lPTIM2 to clock out of HSI16 and prescaler to 16 and thus I think i should get 1 micro tick. Then with ARR set to 1000 we have a 1msec interrupt. Any suggestions as to why the interrupt does not happen?. Thanks.

LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_HSI);//Use clock source as HSI

LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2);//This is enabling the APB1

//Set Interrupt enable

/* Configure the NVIC to handle TIM1 update interrupt */

NVIC_SetPriority(LPTIM2_IRQn,0);

NVIC_EnableIRQ(LPTIM2_IRQn);

/* Time base configuration */

TIM_TimeBaseStructure.ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; /* TIM1 is a 16bit timer */

TIM_TimeBaseStructure.Prescaler =4;

LL_LPTIM_Init(sParam->LPTIMx, &TIM_TimeBaseStructure);

LL_LPTIM_EnableIT_ARRM(LPTIM2);

LL_LPTIM_Enable(LPTIM2);

hal_LPTIM_SetAutoreload(LPTIM2,1000);

LL_LPTIM_OperatingMode(LPTIM2,LL_LPTIM_OPERATING_MODE_CONTINUOUS);

[Balasubramanian vaidhyanathan]

Posted on February 15, 2018 at 20:49

Hi Jan

  I got the LPTIM to work. One thing was I had not turned on HSI clock. The APB clocks were derived out of MSI and I had not noticed if HSI was ON. So now I got it working.