STM32L476 CAN RX interface (FIFO capacity)
Hello to every one,
could anyone clarify something about the capacity of every FIFO stage description?
At datasheet main features, in reception part, there is a:
'Two receive FIFO with 3 stages'
Which is the capacity of every stage? At 42.3.4 there is a description where can be read: '3 complete messages can be stored un each FIFO'.
Does it mean that one message is equivalent, exactly, to one CAN frame or is it a concrete number of bytes per FIFO stage? If it is a concrete number of bytes (so different to the number of bytes of a complete frame) I haven't found this information in any part of the datasheet.
How many bytes every FIFO stage can store? how many bytes a 'complete message' is reffered?
I would like to force an overload for testing purposes and I need to have this issue clarified.
Thanks in advance.
#stm32l4 #can-fifo #stm32l476 #can-rx #can-architecture