STM32L475RC - Clock security system on LSE - LSECSSD is set after power on reset.

[mcoc7n]

Hi,

I'm working with a STM32L475RC. The RTC is sourced by LSE and the CSS on LSE is activated.

On every power on the LSECSSD bit in the backup domain control register is set. This means that the CSS has detected an error on the LSE. Now I'am wondering what kind of errors are signaled by the LSECSSD bit.

When I run the system with CSS on LSE disabled, the RTC runs flawlessly.

What kind of errors are signaled by the LSECSSD bit?

Thanks,

Marco