STM32L43KC: Changing Clock Frequency?

[CLeo.1]

Hey guys, just having the hardest of times changing clock frequency to 80MHz for the system clock and 43MHz for the ADC clock. Every time I try it seems the writing function to registers gets disabled such as RCC->AHB2ENR trying to enable GPIOA and ADC clock enables.

The weirdest thing is I tried it even with the HAL pre-generated code and there's no difference in performance. I am running a digital filter and its still takes the same time as it was on 4MHz assuming the HAL worked in changing the clock frequency. Any Ideas?

Here's the code:

void initClock(){

void initClock(){
 
 RCC->CR |= RCC_CR_MSIRGSEL; // Enable: MSIRANGE in CR
 RCC->CR |= RCC_CRMSIRANGE_6;
 
 RCC->PLLCFGR &= ~(1<<12); //
 RCC->PLLCFGR |= ((1<<13) | (1<<11)); // PLLN = 40
 RCC->PLLCFGR |= (1<<0); // PLLSRC = MSI
 
 RCC->PLLSAI1CFGR |= (1<<25); //PLLSAI1R = 4
 RCC->PLLSAI1CFGR &= ~(1<<12);
 RCC->PLLSAI1CFGR |= ((1<<8) | (1<<9) | (1<<11) | (1<<13)); //PLLSAI1N = 43
 
 RCC->CR |= (1<<24); // Enable: PLL
 while(((RCC->CR) & (1<<25)) == 0); //Wait till PLL is ready
 
 RCC->CR |= (1<<26); // Enable: PLLSAI1
 while(((RCC->CR) & (1<<27)) == 0); // Wait till PLLSAI1 is ready
 
 RCC->PLLCFGR |= (1<<24); // Enable: PLLREN Goes into System Clock 
 RCC->PLLSAI1CFGR |= (1<<24); //Enable: PLLSAI1REN Goes into ADC
 
 RCC->CFGR |= ((1<<1) | (1<<0)); // Switches to the PLL ClCK source
}

[waclawek.jan]

You have to change the FLASH waitstates number (see FLASH_ACR.LATENCY) before switching to higher clock, and maybe also voltage regulator ("range") setting.

JW

[CLeo.1]

Thank you for the reply. See I tried looking into it, please correct me if I am wrong, however with the STM32 Chip I am using it doesnt look like I need to change the wait states? I checked the Flash_ACR register and I guess you can use any wait state for any frequency? The Voltage regulator thats a new one, Ill give it a shot

[CLeo.1]

Just double checked what you said. Correct Ill change it accordingly and Ill let you know. Thank you

[CLeo.1]

Thank you! It worked!

[berendi]

In line 6, bit 12 of RCC->PLLCFGR is reset, and the PLLN field temporarily becomes 0, which is an illegal value according to the reference manual. Try it in one operation:

RCC->PLLCFGR = (RCC->PLLCFGR & ~RCC_PLLCFGR_PLLN) | (40 << RCC_PLLCFGR_PLLN_Pos);

then do the same for PLLSAI1N.

ADC clock source should be selected in RCC->CCIPR