STM32L4 Timer OCxREF reset, Toogle and Gated Mode questions

[BJero.1]

Hi,

On a STM32L476 MCU, I use many timers with various synchronization / outputs combination. I've two problems still remaining :

• On TIM3, the Channel 4 Output compare mode TOOGLE do not seems to work correctly (the GPIO do not toogle, it simply goes from low to high when the timer after the first OC match after the timer is started) although the timer channel is correctly configured because the ADC is correctly clocked from the same timer channel OC match. The same code on the Channel 1 of this timer works (the only one difference is that the channel 1 is not used as trigger input for the ADC block)
• One of the other timers (TIM2 or TIM5, I don't have code right now) configured in gated mode, I'd like to reset the OCxREF of one channel to ensure that this channel output (configured in output compare toogle mode) always start from the same state. I tried to set the output compare mode to 'Force Inactive Level' or 'Force Active Level' but it does not work. The reference manual p1036 says that this can be used to force the OCxREF independantly of the output compare registers and counter. However, this do not seems to work on my software. Does it still work when the timer is 'not running' (i.e when the timer is not gated) ?
• One last question about gated timers. I'd like to be able to inform upper layers of my software when the trigger interrupt hit, with the counter enable status. In the interrupt handler, I read the content of the CR1 register, but the CEN bit is always set to 1 (which is a requirement for the gated mode to work as specified in reference manual p1061. Is there any way to have the 'real' state of the timer ?

Regards, Jerome

[waclawek.jan]

> On TIM3, the Channel 4 Output compare mode TOOGLE do not seems to work correctly

OCxRef is output from comparator and input to the "pin control" stage which performs PWM or toggle, so if that is not set properly to Toggle, pin will "not work" while OCxRef still can work correctly.

Read out and check/post TIM and relevant GPIO registers content.

> tried to set the output compare mode to 'Force Inactive Level' or 'Force Active Level' but it does not work.

Ditto.

> Does it [the force *** level] still work when the timer is 'not running' (i.e when the timer is not gated) ?

Yes.

(Btw. I believe "gated" refers to the state when the counter does not run.)

> Is there any way to have the 'real' state of the [gated] timer ?

No. You have to infer it from the state of signal which is source of the slave-mode controller.

JW

[BJero.1]

Hi,

Thanks you and sorry for being slow to answer. Well, I've not been able to make the channel 4 of the TIM3 to work properly. Maybe it is related to the trigger connection to the DAC. GPIOs are correctly set, and timer channel configuration is the exact same as channel 1. Anyway that's not a big problem because I can set the channel 1 for debug purpose. The reset of the OCREF indeed work.

Regards,