STM32L4 Nucleo LSE drift

[Gerardo GALLUCCI]

Posted on May 07, 2018 at 21:40

Hi all,

is there a way to improve LSE drift on L4 Nucleo board? Or all I can do is to migrate to another crystal with higher precision?

Thanks, and regards

jerry

[waclawek.jan]

Posted on May 07, 2018 at 21:47

is there a way to improve LSE drift on L4 Nucleo board?

What drift? How do you know it's drifting?

JW

[Gerardo GALLUCCI]

Posted on May 07, 2018 at 21:50

RTC set by GPS, and after 24h time is wrong (a little bit). Better than LSI used before.

[waclawek.jan]

Posted on May 07, 2018 at 22:26

Little bits can be compensated by calibration.

Read the RTC smooth digital calibration chapter in RM.

JW

[Amel NASRI]

Posted on May 09, 2018 at 17:59

Hi

Gallucci.Gerardo

‌,

Please refer to

http://www.st.com/content/ccc/resource/technical/document/application_note/c6/eb/5e/11/e3/69/43/eb/CD002216pdf/files/CD002216pdf/jcr:content/translations/en.CD002216pdf

: 'Oscillator design guide for STM8AF/AL/S and STM32 microcontrollers'.

if you are searching for minimum drift, you need to select Crystals with 5pF of CL they have teh best pullability factor versus the one of 6pF or 7pF that are more optimized for power consumption.( our nucleo board)

as well you need to adapt the right drive mode as our STM32L4 is able to have 4 drive modes from High to low depending on the usage : low drift or low power.

Also, CL1/CL2 capacitors should be trimmed at first design and PCB build to compensate the Cs ( stray capacitance) including the pads PC14/PC15 to reach the closest frequency of 768KHz , you can observe that at MCO level during this trimming and an universal counter.

-Amel