STM32L1 HSE/PLL failure

[Kuikui]

Posted on July 11, 2016 at 13:56

Hi,

2 questions about HSE/PLL :

1. Supposing the HSE/PLL is running fine, is it possible that it suddenly stops running without any reason ?

2. If yes, what happens about the SYSCLK ? Does it switch to HSI ?

Thank you for your help.

Best regards,

Vincent.

[jpeacock23]

Posted on July 11, 2016 at 16:46

A crystal is a mechanical device.  It vibrates, it can fail.  Or it can fail if the caps are incorrect, or any number of reasons.  If you have CSS (clock security system) enabled the controller will fall back to the reset oscillator, 2.048MHz MSI, PLL off.  You can trap this event with the NMI vector and switch to HSI with a PLL to get back to the 32MHz clock rate, although accuracy won't be as good as HSE.  You can't use the MSI with the PLL.

You can do the same with the RTC, enable CSSLSE and an LSE failure will trigger an RTC interrupt.  You can fall back to the LSI oscillator at that point.

  Jack Peacock

[Kuikui]

Posted on July 12, 2016 at 10:33

Hi,

Thank you for your answer.

''If you have CSS (clock security system) enabled the controller will fall back to the reset oscillator, 2.048MHz MSI, PLL off.''

What if the CSS is not enabled ?

I guess this is written in the reference manual, but can't find it.

Best regards,

Vincent.

[jpeacock23]

Posted on July 12, 2016 at 13:27

Without a clock the processor stops.  That's why the CSS is there, to make sure the controller keeps going.

[Walid FTITI_O]

Posted on July 12, 2016 at 18:41

Hi VDM,

The clock security system (CSS) monitors HSE crystal clock source failures when HSE is used as the system clock. If the HSE clock fails due to a broken or disconnected resonator or any other reason, the clock controller activates a stall-safe recovery mechanism by automatically switching SYSCLK to the HSI with the same division factor as that used before the HSE clock failure. Once selected, the auxiliary clock source remains enabled until the microcontroller is reset. The application can enable the clock security system by setting the CSSEN bit in the Clock security system register (CLK_CSSR). For safety reason, once CSS is enabled it cannot be disabled until the next device reset.

Check the STM32L1 reference manual RM0031 at this

http://www.st.com/content/ccc/resource/technical/document/reference_manual/2e/3b/8c/8f/60/af/4b/2c/CD00218714.pdf/files/CD00218714.pdf/jcr:content/translations/en.CD00218714.pdf

, page 95, section 9.8 Clock security system (CSS).

-Hannibal-