STM32L1 FLASH ACR Latency Configuration

[AumDhabalia]

Hi,

I want to configure STM32L152RE board to max speed of 32MHz using HSE 8MHz. As per reference manual, flash latency can be configured only in 64 bit read operations. I want to use 32bit read operation for low power consumption. I am confused on how to use the board in bare metal programming specifically for flash latency part. I am using platform.io and want to initialize the RCC using HSE and PLL. I need guidance for RCC initialization and flash latency configuration portion.

[Ozone]

>  I want to use 32bit read operation for low power consumption. 

Unless I got something wrong, there is no such option - not that it would save power anyway.
“Flash read” is basically synonymous with “instruction read”, and the 64-bit or 128-bit Flash read operations fill the cache (a.k.a. ART) which feeds the core instruction pipeline.

You would need to configure the required number of waitstates for the core clock frequency you choose, before enabling HSE. Those are listed in the datasheet, usually. Setting a too low number will cause the core to most likely crash when enabling the higher clock.

Halving flash read / instruction read throughput by halving read size would only slow down execution, and result in higher power consumption through longer on times.
Better use sleep modes for lower consumption.

[waclawek.jan]

​@Ozone ,

The ‘L1 is a very different beast from other STM32, and indeed, it has an option to fetch 32-bit words from FLASH, for slow execution at low clock frequencies, in exchange for presumably lower power consumption, although the DS does not specify, how much exactly.

​@AumDhabalia ,

The requirements for FLASH operation are detailed in RM0038 chapter 3.3.1 Relation between CPU clock frequency and Flash memory read time, and for 32-bit operation, number of waitstates must be 0, which means, the system clock frequency must be according to the 0WS row of Table 12, i.e. if the internal voltage regulator is set to Range 1, it’s max. 16MHz (for the settings of internal voltage regulator, see 5.1.5 Dynamic voltage scaling management)

JW

[Ozone]

> The ‘L1 is a very different beast from other STM32, and indeed, it has an option to fetch 32-bit words from FLASH, …

Thanks, interesting to know.
However, it seems this feature was not too successful, as these L1 devices were rather quickly superseded by other MCU families.

And I still very much doubt that the reduced fetch width improves overall consumption, instead of increasing it through prolonged runtime.

[waclawek.jan]

This is described in detail in the two RM chapters I mentioned above. 

I’m not sure if you can find a ready-made example. Try perhaps having a look at some older SPL-based ones, maybe in their startup code. I personally have no experience with the ‘L1 family.

JW

[Ozone]

> Try perhaps having a look at some older SPL-based ones, maybe in their startup code.

The L1 family is definitely covered by SPL-based code.
Update of “legacy” MCU example code to Cube was always lacking, not sure if it even exists for L1 devices.
But the SPL packages are still available for download.

I have a L152 discovery, but found it lacking the performance for many of my projects.