You're confusing peripheral level functionality. The DMA controller has a HT (Half-Transfer) and TC (Transfer Complete) indication allowing for a buffer to be split in a ping-pong fashion, and defining an active and inactive portion the IRQ Handler or Callback can manage without interfering with the transfer.
In the U(S)ART context TC means Transmit Complete, that all the bits in the word have crossed the wire. TXE signals when the "buffer" is empty usually as the first bit hits the wire as the buffer is moved into the shift register to move the bits across the wire.
To keep the U(S)ART busy it's usually best to fill based on TXE to insure continuity, and provide about a byte time to service the request
Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..