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amar_1
Visitor II
March 18, 2026
Solved

STM32H7S78-DK. hangs and eventually Hard Faults writing to XSPI NOR flash

Currently I am working on STM32H7S78-DK board, In that I am trying to save some data in External flash which will be read over every boot up but while trying to write in specific memory location it will hit to hard fault. I would like to seek clarification regarding write and erase operations on external NOR flash while operating in XIP (memory-mapped) mode on the STM32H7S78-DK.
Current Setup:
  • The application is executed directly from external NOR flash (mapped at 0x70000000 via XSPI).
  • Memory-mapped (XIP) mode is enabled for instruction execution.
  • Read operations from external flash are working as expected.
Observed Issue:
  • During erase/write operations, the system encounters hangs and eventually enters a Hard Fault condition.
Understanding of the Issue:
  • Erase/program operations require switching the XSPI interface from memory-mapped mode to indirect/command mode.
  • During this transition:
    • External flash is not available for instruction fetch.
    • The CPU continues attempting to execute code from the same external flash.
    • This results in instruction fetch conflicts, leading to system instability (hangs/HardFault).
  • Additional factors increasing complexity:
    • Interrupts and ISRs may still reside in external flash.
    • RTOS-based execution further increases the likelihood of conflicts.
  • Whether write/erase operations on the same external NOR flash are supported during XIP execution.
  • Recommended approach to safely perform these operations:
    • Executing flash drivers from internal RAM
    • Relocating interrupt handlers to RAM
    • Any required restrictions or best practices
  • Availability of any reference examples or application notes specific to STM32H7S78-DK.
mƎALLEm
mƎALLEmBest answer
ST Technical Moderator
March 19, 2026

Hello,

Almost the same question asked in this post.

You can't write to that memory while executing from it. You said it yourself: you need to switch from memory-mapped mode to indirect/command mode so the instruction fetch is no more available.

Need either:

- To use two external XSPI memories: one for execution and one for the data storage so you don't have a such issue. Refer to the AN6228 "How to implement XSPI read-while-write feature on STM32 MCUs"

- Or to execute that code that writes to the external flash from the internal Flash (could be a bit tricky). 

Hope I've answered your question.

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.
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2 replies

mƎALLEm
mƎALLEmBest answer
ST Technical Moderator
March 19, 2026

Hello,

Almost the same question asked in this post.

You can't write to that memory while executing from it. You said it yourself: you need to switch from memory-mapped mode to indirect/command mode so the instruction fetch is no more available.

Need either:

- To use two external XSPI memories: one for execution and one for the data storage so you don't have a such issue. Refer to the AN6228 "How to implement XSPI read-while-write feature on STM32 MCUs"

- Or to execute that code that writes to the external flash from the internal Flash (could be a bit tricky). 

Hope I've answered your question.

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.
Hamady
Associate III
March 23, 2026

Hello 

@amar_1 @mƎALLEm 

 

For my side i was wondering how to do a FW update ( so write data to XSPI1 while XIP) .

 

I checked the application note AN6228 but it is so hard to configure it because it require to have 2 config one with flash + psram and one with only flash and 2 port multiplexed.

 

So for that i write from the internal flash code (BOOT) to XSPI1 . It is really easy to do it you can take exemple of the EXTMEM functions used in the memory manager included in boot. Or you can check exemple in cubeh7rs to write to flash with xspi commands.

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