STM32H7S3L8H6: max fCPU with AXI-SRAM ECC enabled (DS14359 Rev 6, Table 26, footnote 8)
Device: STM32H7S3L8H6
Datasheet DS14359 Rev 6, Table 26 "General operating conditions", gives for
fCPU (CPU clock frequency):
VOS low max 400 MHz
VOS high max 600 MHz (8)
footnote (8): "With ECC disabled"
We cannot find any stated maximum for fCPU with the AXI-SRAM ECC ENABLED
(user option byte ECC_ON_SRAM = 1). RM0477 mentions ECC only in connection
with AXISRAM4 wait states, not with a frequency limit.
This matters to us because ST's own OEMuRoT/BL2 reference code
(OEMIROT_USER_SRAM_ECC in boot_hal_cfg.h) requires that option byte and
refuses to boot without it, so an application using the STiRoT + OEMuRoT
secure boot chain necessarily runs with ECC permanently enabled.
Operating conditions on our side: VOS high (range 0), LDO supply,
TJ <= 105 degC.
Questions:
1. What is the maximum fCPU for this device with ECC_ON_SRAM = 1?
2. In the OEMuRoT reference code, SetSysClock() selects 380 MHz with the
comment "to be functional with all hardware configurations (ECC_ON_SRAM
enabled, no internal regulator) and with the full range of temperature
(Tj up to 125 degrees)". Is 380 MHz the ECC-enabled limit, or is it the
intersection of several worst cases? If the latter, what limit applies
for ECC enabled at VOS high with TJ <= 105 degC?
