In a multi-core controller, a hardware mailbox peripheral is used to pass messages between cores. In your case, with a single M7 core, there are no hardware mailboxes. A software-based mailbox is essentially a single-entry queue. For a CAN protocol stack, incoming RX messages are removed from the CAN hardware RX FIFO and placed in the queue during the RXFIFOx interrupt. The CAN protocol task unblocks when a message is placed in the queue. The task removes the message and processes it through the protocol services.
The CAN RX and TX buffers are based on hardware and have a fixed size and functionality. If you set up the CAN filters properly you can route incoming CAN messaged to either FIFO0 or FIFO1, a two-level priority scheme. Depending on what RTOS you use any message in the high priority FIF00 buffer is inserted at the head of the CAN message queue, so it is handled out of sequence. FIFO1 message are inserted at the queue tail and are handled in the order they arrive.
I don't recommend a single entry, mailbox type queue to store and forward incoming CAN messages. If the CAN protocol stack is busy there's an excellent chance RX messages can be dropped when the RX FIFO overflows. I use FreeRTOS and a queue with multiple entries to avoid this. FreeRTOS queues also support inserting new messages at the head of the queue.
Keep in mind some complexities when using prioritized messages. For example, you can receive an emergency shut down for a pump, followed by an earlier normal status message from the same node.
Also, if you have two writers to a single queue, you might want to set the interrupt priority for both RXFIFO interrupts to the same level, preventing a queue write from being pre-empted. In FreeRTOS you can set up two queues to avoid this problem, but the protocol task has to check both queues when unblocked, and an event group has to be used to wake up the task. If you expand your application to fault tolerance, with dual CAN buses, there are some advantages to multiple queues.
And no, mailboxes are not like the TX and RX buffers on the CAN peripheral. The CAN FIFOs are hardware specific; a mailbox is a type of inter-task queue.
Jack Peacock