STM32H74x Errata 2.5.3 QuadSPI - is the provided workaround feasible for read operation ?

[VZ.1]

The errata suggest to "insert a dummy phase with at least two dummy cycles" when using indirect data read mode.

However, according to the documentation of the dummy cycle phase (AN4760 rev 3, section 3.1.4 and figure 8 ) states that in the dummy phase the clock continues to oscillate. So if used during read transaction, the data would be clocked in from the device and subsequently lost.

Moreover, the data lines 2 and 3 are driven during these cycles.

Am I reading this wrong, or is the workaround not suitable for the intended purpose of read operation ?

[Andreas Bolsch]

From the RM: "The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories."

For a flash memory, indirect read with data phase only makes little sense, even in so-called XIP-mode at least address phase is required additionally.

So the problem does appear only if the QSPI is used in a way it was not designed for ...

[VZ.1]

Well, if implemented as designed (without the errata bugs), it would have been extremely useful in interfacing to modern multi-lane ADC and DAC ICs.

probably the only option as is would be to switch to different CPU or insert FPGA in the middle :unamused_face:

[berendi]

There are 10 SPI interfaces (counting USARTs too) on the STM32H743, how many channels do you need?

Reading GPIO->IDR with DMA triggered by a timer which also provides the clock on a PWM output, or receives the external clock signal on a capture input would work too.

I think FMC too could be abused to provide a multi-channel spi like interface, but the "clock" phase might be wrong. An external inverter could cure that though.