STM32H745 SDMMC DMA Rx Overrun/Tx Underrun

[Joyabb]

Hi,

I am working on STM32H745 discovery board and trying to configure the onboard 4GB eMMC flash over SDHC1 interface. I am loading default discovery board configuration by the CubeMx configuration, which sets both M7 and M4 and all AHB buses to run at 64MHz (STM32H7 CubeMx Repository v1.8.0).

I am configuring the SDMMC peripheral clock to 200MHz and setting clockdiv to 4, this will provide 25MHz clock to the eMMC. My application is running on M7. I want to utilize the IDMA for read/write and using HAL_MMC_ReadBlocks_DMA and HAL_MMC_WriteBlocks_DMA APIs. By using this configuration, the DMA interrupts are resulting in Rx Overrun and Tx Underrun errors.

I ran the MMC/DMA example for the discovery board which sets eMMC clock to 50MHz, M7 at 400MHz, M4 at 200MHz. The HCLK for D1 Domain AXI and AHB3 peripherals , D2 Domain AHB1/AHB2 peripherals and D3 Domain AHB4 peripherals at 200MHz.

The APB clock dividers for D1 Domain APB3 peripherals, D2 Domain APB1 and APB2 peripherals and D3 Domain APB4 peripherals to run at 100MHz. This example seems to be buggy and does not read correct number of blocks from eMMC.

But with the same example if I change the clockdiv to give 25MHz clock to eMMC, the DMA operations are working fine and the example runs as expected.

With this observations, I need help answering few of questions.

1. What is the reason for the MMC/DMA example of STM32H745 Discovery board does not run with 50MHz eMMC clock but runs fine when it is changed to 25MHz?
2. What could be the reason for the overrun/underrun issues with my project?
3. Is there a connection between CPU and AHB bus speeds with IDMA and eMMC clock speed?
4. Is there a straight forward documentation available which simplifies the clock related mysteries?

Thanks,

Joyab

[Joyabb]

I got things working. Following are my findings.

1. I still could not figure out the reason behind MMC/DMA example not working with 50MHz eMMC clock. But as I mentioned 25MHz clock works fine,
2. The DMA issues were mainly related to the RAM being used for Data buffers. I changed the data buffer locations to DMA compatible RAM, and it fixed the problem.
3. The CPU clock and AHB bus clocks at 64MHz works fine with eMMC and IDMA. No issues here.
4. I went through the reference manual and was able to get a fair bit of idea about the clocks.

After fixing all MMC level issues, I was able to run the FatFS just fine with cache disabled on CM7. The cache enable still has some issues, even with the ST provided examples.

I came across this post which help me fix the ST example bug related to cache maintenance.

https://community.st.com/s/question/0D50X00009XkWmR/sd-card-memory-corruption-due-to-overly-aggressive-cache-maintenance?t=1612158756960

[CNhan.1]

Hi Joyabb

​

I ran into the same issue as you with getting the underrun/overrun error when transmit data using HAL_MMC_WriteBlocks_DMA and HAL_MMC_ReadBlocks_DMA (or even without the DMA protocol, just transmit a block of 512 bytes, we run our SDMMC application as 25Mhz). I just work around by enable the Hardware flow control but this doesn't seem to work with DMA.

I read your recommendation and could not fully understand this line "The DMA issues were mainly related to the RAM being used for Data buffers. I changed the data buffer locations to DMA compatible RAM, and it fixed the problem".

I would really appreciate it if you could explain this to me in more detail.

Thank you very much.​

​

[Joyabb]

There are various RAM blocks available in the MCU, and not all of the RAM are accessible by all DMA bus masters. For E.g. STM32H7 series, AXI SRAM is not accessible by BDMA. So if you try to use a data buffer from AXI SRAM (RAM Base address 0x24000000) as source or destination buffer for DMA transfer with BDMA, the DMA controller will give overrun/underrun error. You need to check the DMA controller and RAM accessibility from the MCU reference manual and ensure you are using correct RAM for DMA transfer.