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Franzi.Edo
Senior
July 5, 2019
Solved

stm32H743Y vs stm32H743V

  • July 5, 2019
  • 3 replies
  • 1372 views

Dear all,

I am facing to a stm32h743 issue. I have a Nucleo with the stm32H743 Rev Y that work perfectly. Now, I just tried the new Nucleo equipped with the stm32H743 Rev V. As expected, my previous code (Rev Y) does not work on the new device (Rev V). I noticed that it should be a Flash speed problem (if I slow down the PLL for the cpu clock from 400-MHz to around 100-MHz, my new board works). Now, the documentation of ST is really not clear about the procedure to set-up the Rev V. It seems I have to change "some" registers but the procedure is not evident. Any suggestion about how to set-up the Flash parameters for the stm32H743 Rev V?

Thank's

Edo

This topic has been closed for replies.
Best answer by Tesla DeLorean

I believe this should work

/**
 * @brief System Clock Configuration
 * The system Clock is configured as follow :
 * System Clock source = PLL (HSE BYPASS)
 * SYSCLK(Hz) = 400000000 (CPU Clock)
 * HCLK(Hz) = 200000000 (AXI and AHBs Clock)
 * AHB Prescaler = 2
 * D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)
 * D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)
 * D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)
 * D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)
 * HSE Frequency(Hz) = 8000000
 * PLL_M = 4
 * PLL_N = 400
 * PLL_P = 2
 * PLL_Q = 4
 * PLL_R = 2
 * VDD(V) = 3.3
 * Flash Latency(WS) = 4
 * @param None
 * @retval None
 */
static void SystemClock_Config(void)
{
 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 HAL_StatusTypeDef ret = HAL_OK;
 
 /*!< Supply configuration update enable */
 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
 
 /* The voltage scaling allows optimizing the power consumption when the device is
 clocked below the maximum system frequency, to update the voltage scaling value
 regarding system frequency refer to product datasheet. */
 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* SCALE0 for 480 MHz */
 
 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
 
 /* Enable HSE Oscillator and activate PLL with HSE as source */
 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
 RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 
 RCC_OscInitStruct.PLL.PLLM = 4;
 RCC_OscInitStruct.PLL.PLLN = 400;
 RCC_OscInitStruct.PLL.PLLFRACN = 0;
 RCC_OscInitStruct.PLL.PLLP = 2;
 RCC_OscInitStruct.PLL.PLLR = 2;
 RCC_OscInitStruct.PLL.PLLQ = 4;
 
 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
 ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
 if(ret != HAL_OK)
 {
 while(1) { ; }
 }
 
/* Select PLL as system clock source and configure bus clocks dividers */
 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
 
 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 if(ret != HAL_OK)
 {
 while(1) { ; }
 }
}

3 replies

Tesla DeLorean
Tesla DeLoreanBest answer
Guru
July 7, 2019

I believe this should work

/**
 * @brief System Clock Configuration
 * The system Clock is configured as follow :
 * System Clock source = PLL (HSE BYPASS)
 * SYSCLK(Hz) = 400000000 (CPU Clock)
 * HCLK(Hz) = 200000000 (AXI and AHBs Clock)
 * AHB Prescaler = 2
 * D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)
 * D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)
 * D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)
 * D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)
 * HSE Frequency(Hz) = 8000000
 * PLL_M = 4
 * PLL_N = 400
 * PLL_P = 2
 * PLL_Q = 4
 * PLL_R = 2
 * VDD(V) = 3.3
 * Flash Latency(WS) = 4
 * @param None
 * @retval None
 */
static void SystemClock_Config(void)
{
 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 HAL_StatusTypeDef ret = HAL_OK;
 
 /*!< Supply configuration update enable */
 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
 
 /* The voltage scaling allows optimizing the power consumption when the device is
 clocked below the maximum system frequency, to update the voltage scaling value
 regarding system frequency refer to product datasheet. */
 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* SCALE0 for 480 MHz */
 
 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
 
 /* Enable HSE Oscillator and activate PLL with HSE as source */
 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
 RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 
 RCC_OscInitStruct.PLL.PLLM = 4;
 RCC_OscInitStruct.PLL.PLLN = 400;
 RCC_OscInitStruct.PLL.PLLFRACN = 0;
 RCC_OscInitStruct.PLL.PLLP = 2;
 RCC_OscInitStruct.PLL.PLLR = 2;
 RCC_OscInitStruct.PLL.PLLQ = 4;
 
 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
 ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
 if(ret != HAL_OK)
 {
 while(1) { ; }
 }
 
/* Select PLL as system clock source and configure bus clocks dividers */
 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
 
 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 if(ret != HAL_OK)
 {
 while(1) { ; }
 }
}

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Linas L
Senior
July 7, 2019

Double check if it has same speed crystal for HSE.

Also V version can go up to 480MHz (i think)

Franzi.Edo
Senior
July 7, 2019

Thank you Clive and Linas.

Problem solved. It was enough to add the following instructions before the PLL set-up. The Clive code was helpful. Thank's

// Only for Rev. V
 
	PWR->CR3	 &= ~(PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
	PWR->CR3	 |= PWR_CR3_LDOEN;
 
	PWR->D3CR	 &= ~PWR_D3CR_VOS;
	PWR->D3CR	 |= PWR_D3CR_VOS_1;

Franzi.Edo
Senior
July 7, 2019

forgotten one line ...

// Only for Rev. V
 
	PWR->CR3	 &= ~(PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
	PWR->CR3	 |= PWR_CR3_LDOEN;
 
	PWR->D3CR	 &= ~PWR_D3CR_VOS;
	PWR->D3CR	 |= PWR_D3CR_VOS_1;
 
	while ((PWR->D3CR & PWR_D3CR_VOSRDY) == 0);	 // Waiting for the vos ready