[STM32H743VI, RM0433] Is the formula to calculate the WWDG timeout wrong?

[Andlev]

I have recently faced with problem that the real timeout and calculated aren't equal.

The formula is described as in the screenshot below.

But the WWDG initiates a reset when the counter (T[5:0]) changes value from 0x40 to 0x3F. Then we have only 128 - 64 (0x40) counts until a reset occurred. Shouldn't the formula be like t_wwdg = t_pclk * 4096 * 2 ^ (WDGTB[2:0]) * (T[5:0] + 1 - 0x40) ?

[Danish1]

One thing that you don't seem to have spotted is that you write T[6:0] to the counter, not T[5:0] with T[6] always set*, but the formula gives the timing from T[5:0].

And it is when bit 6 drops from 1 to 0 that the WWDG fires.

T[5:0] cannot express 0x40 -- it needs to be T[6:0]

So a long-as-possible counter write of 0xFF will have 0x3F in T[5:0]

*And WDGA set which is in bit 7

Hope this helps,

Danish

[Andlev]

Indeed! I didn't expected this at all. Then this topic should be closed I think, since there is no mistake.

Tanks for clarification, Danish!