STM32H743 dual ADC w DMA

[Handzic.Dirk]

Posted on June 21, 2018 at 11:37

The original post was too long to process during our migration. Please click on the attachment to read the original post.

[Tesla DeLorean]

Posted on June 21, 2018 at 13:31

Sounds like a cache coherency issue.

[Handzic.Dirk]

Posted on June 21, 2018 at 13:55

That is why I added

SCB_InvalidateDCache_by_Addr((uint32_t *) &sample_buffer[0], 4*P_SAMPLES);

to the transfer complete handling. Is there any better way? Initially I had a call to SCB_InvalidateDCache_by_Addr() at half complete transfer as well but due to the high sample rate I had to remove it.

[Tesla DeLorean]

Posted on June 21, 2018 at 14:49

>>Is there any better way?

Use an uncached/unbuffered memory region?

Change the MPU configuration for the region you are using, and expect to act on externally?