STM32H743 - Clarification needed on simultaneous usage of two FD-CAN peripherals

[wildfireheart]

I need clarification on part 2.14.2 of Errata - Wrong data may be read from Message RAM by the CPU when using two FDCANs. As a workaround, it's stated there that "To avoid concurrent read accesses between the CPU and FDCANs, use only one FDCAN at a time."

I do not understand, whether this means, that only one FDCAN can work at the same time and second one must be off (effectively chip having only one functional FDCAN), or if it means that you merely need to avoid reading from both peripherals "at the same time".

I cannot get two FDCANs going whatever I try. Even bog standard configuration copied from examples doesn't work. I have them configured to use different message RAM addresses of course.

EDIT1: If anybody needs this, I got it partially working. FDCAN clock was set to 400 MHz and Cube was fine with it, 55.3.5 of Reference manual states, that fdcan_ker_ck is designed to operate up to 80 MHz, so if FDCAN works but is acting weird, you could have it overclocked. I'm still getting some hard faults, so I'll edit this again when I solve it.

[RMart.0]

Thanks for the tip on the FDCAN max frequency, I could replicate it with the H750 in MX 5.5.0. This should definitely be corrected in CubeMx by having a check for max freq for the peripheral.

As to the HardFaults, if it helps anything, I have 2 CAN modules running concurrently on a H750, albeit both are configured as classic (not FD). I am able to receive and send without issues, via HAL, DMA style, and filtering enabled and shared between the 2 modules.

[Tesla DeLorean]

>> I'm still getting some hard faults,

Yes, probably unrelated. Use a proper Hard Fault Handler so you can get actional diagnostic information, and inspect/analyze the faulting code.

Most likely stack/heap collision, cache coherency, or alignment issues. Even the CM7 with fault on unaligned double-word reads, ie LDRD/STRD and 64-bit double related code. This can be a particular issue unpacking byte aligned structures.