STM32H730VBT6 SPI port mappable to OCTOSPI interface?

[pkoevesdi]

We have a custom board prototype with a STM32H730VBT6 (LQFP100 package) and a SPI NOR flash memory.

Sadly, this not connected to the OCTOSPIM_P1 port, but to the SPI1_NSS, SPI1_SCK, SPI1_MISO, SPI1_MISO (PA4, PA5, PA6, PB5) port (so, ony 2 data lines are connected, classic SPI).

Now, our application will not fit into internal flash (nor into RAM), so we are captive to use external memory for our program. How can we solve it, except make a new board? Some questions more in detail:

1. Can SPI1 be mapped somehow to OCTOSPI1?

2. Is it (physically or software-wise) possible at all to use that SPI1 connected chip as memory?

    I'd probably would have to reprogram the whole memory protocol (command, address, alternate bytes and data phase...)?

3. What features are possible: DTR? Dual-line SPI? Memory-mapped mode?

    (I think, at least the latter is impossible, if the answer to 1. is no.)

4. Is it possible to execute-in-place from that memory?

    (I think not, if it cannot be brought into memory-mapped mode.)

 

Can You shed some light, and maybe also confirm or refute my assumptions?

Thank You very much!

[Pavel A.]

@tjaekel Can you write to the PSRAM in memory-mapped mode?

 

[tjaekel]

Yes, I can.
Just to configure the also the Write command instruction for Memory Mapped mode.
Just: to think about how to "handle" the page wrap (chip wraps to begin of page if a page boundary is crossed).
When caches are enabled - it should not happen that a page boundary is crossed (Cache Line Size).