STM32H723/735 external hyperram access

[DMast.1]

Good morning,
I'm writing here to ask for help resolving a problem we're having with a custom board that uses a HYPERRAM bus and external RAM chip. Specifically, if Infineon S70KL1282GABHV020 memory is installed on the board, we can easily access byte/word/dword reads and writes, even at a 166MHz clock speed.

Needing more external RAM, we installed the ISSI IS66WVH64M8DBLL-166B1LI chip (64MB).However, we can no longer access it properly. Specifically, if we try to access bytes at even addresses, the system seems to work. If we access odd addresses, however, we start to experience access errors. Even lowering the clock frequency to 25MHz, the problem persists.

To avoid layout issues, we replaced the hyperram on the STM32H735-DK evb with the ISSI chip, and the behavior is similar.
Below is part of the hyperbus initialization code and the code we use for testing the entire memory.

  /* Initialize OctoSPI ----------------------------------------------------- */
  OSPIHandle.Instance = OCTOSPI2;
  HAL_OSPI_DeInit(&OSPIHandle);

  OSPIHandle.Init.FifoThreshold         = 4;
  OSPIHandle.Init.DualQuad              = HAL_OSPI_DUALQUAD_DISABLE;
  OSPIHandle.Init.MemoryType            = HAL_OSPI_MEMTYPE_HYPERBUS;

  OSPIHandle.Init.DeviceSize = POSITION_VAL(OSPI_RAM_SIZE);

  OSPIHandle.Init.ChipSelectHighTime    = 4;
  OSPIHandle.Init.FreeRunningClock      = HAL_OSPI_FREERUNCLK_DISABLE;
  OSPIHandle.Init.ClockMode             = HAL_OSPI_CLOCK_MODE_0;
  OSPIHandle.Init.WrapSize              = HAL_OSPI_WRAP_NOT_SUPPORTED;
  OSPIHandle.Init.ClockPrescaler        = 2;
  OSPIHandle.Init.SampleShifting        = HAL_OSPI_SAMPLE_SHIFTING_NONE;
  OSPIHandle.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;//>> HAL_OSPI_DHQC_ENABLE;
  OSPIHandle.Init.DelayBlockBypass      = HAL_OSPI_DELAY_BLOCK_USED; //>>HAL_OSPI_DELAY_BLOCK_USED;
  OSPIHandle.Init.ChipSelectBoundary    = 0;
  OSPIHandle.Init.MaxTran               = 0;
  OSPIHandle.Init.Refresh               = 400;

  if (HAL_OSPI_Init(&OSPIHandle) != HAL_OK)
  {
    Error_Handler() ;
  }


  /* Configure the Hyperbus to access memory space -------------------------- */
  sHyperbusCfg.RWRecoveryTime   = 4;
  sHyperbusCfg.AccessTime       = 6;
  sHyperbusCfg.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE;
  sHyperbusCfg.LatencyMode      = HAL_OSPI_FIXED_LATENCY;

  if (HAL_OSPI_HyperbusCfg(&OSPIHandle, &sHyperbusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    Error_Handler();
  }

  /* Memory-mapped mode configuration --------------------------------------- */
  sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
  sCommand.AddressSize  = HAL_OSPI_ADDRESS_32_BITS;
  sCommand.DQSMode      = HAL_OSPI_DQS_ENABLE;
  sCommand.Address      = 0;
  sCommand.NbData       = 1;

  if (HAL_OSPI_HyperbusCmd(&OSPIHandle, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    Error_Handler();
  }

  sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
  sMemMappedCfg.TimeOutPeriod     = 0x34;       /* circa 50 cicli */
  if( HAL_OSPI_MemoryMapped(&OSPIHandle, &sMemMappedCfg) != HAL_OK)
  {
    Error_Handler();
  }


#define DATA_OFFSET						2u

	errors = 0;
	mod1errors = 0;
	uint8_t *pzMem = (uint8_t*) OCTOSPI2_BASE;
	uint32_t total_bytes = 64u * 1024u * 1024u;

	for (i = 0; i < 100; i++)
	{

		for (uint32_t zIndex = 0; zIndex < total_bytes; zIndex += DATA_OFFSET)
		{
			pzMem[zIndex] = (uint8_t) (zIndex & 0xFF);
			__asm("NOP");
		}

		for (uint32_t zIndex = 0; zIndex < total_bytes; zIndex += DATA_OFFSET)
		{
			uint8_t read_val = pzMem[zIndex];
			uint8_t expected_val = (uint8_t) (zIndex & 0xFF);

			if (read_val != expected_val) {
				modAddress = zIndex % 8;
				errors++;

				if (modAddress == 1) {
					mod1errors++;
				}

			}

			__asm("NOP");
		}

	}

if  DATA_OFFSET                        2u → Even read/write access

if  DATA_OFFSET                        1u → Odd/Even read/write access

For your convenience, I am also attaching the Hyperram ISSI datasheet. issue. I'm available if anyone needs further information to understand what's going on. My guess is that some HYPERBUS configuration parameter is incorrect when I access the higher-capacity RAM.

I thank in advance anyone who can help resolve this