STM32H7 SPI CS Question

[AMerc.8]

I have been having a bit of trouble getting an SPI CS line to behave as I expect it should. I have attached a snippet from the technical reference manual below that describes the operation modes of the CS line:

I am currently trying to send packets of 24bits on SPI4 which has a max packet size of 16bits. Since the hardware mode uses the packet size to set the EOT flag and the EOT flag is used to pull the CS line high I cannot send a continuous 24bit packet using the hardware mode.

I figured alternatively I would be able to use the software mode and configure the CS line as a GIO and manually pull it low before beginning a DMA SPI transmit and pulling it high again using the SPI_DMATransmitCplt() call back function. When I try to do this I find that there several points where the CS line is pulled high for 20ns during the transmission. I have attached a logic analyzer screenshot below for reference:

When I debug with a break point within the DMA call back function I find it it isn't called at any point. It seems that the SPI driver is still setting the CS line high even in software management mode. Is there something I am misunderstanding about how this driver behaves?

[AScha.3]

20ns spikes random... spikes are very short - maybe to short, to come from cpu/port action.

is your logic analyzer clocked at 50 or 100 M ? then this is just, what he can show, for any 20....1ns spike.

your spikes happen all at the time, clk AND mosi going low - so i would assume , this is some ground bounce artifact and your wires on this spi are too long, have bad ground or the point of analyzer ground connection is less than optimal.

improve this first.

to reduce the strong effects of superfast switching, set spi port speed lower, then check again.

in cube ->

[AMerc.8]

The logic analyzer I am using is 50M and I currently have the SPI transmission speed set to 390.625 KBits/s. I have moved the ground from the supply to the chip itself and I am getting the same issue. I will try swapping the cables out for something shorter and I will get back to you.

Right now I have the MOSI and SCK lines set to low for max output speed and the CS line set to very fast as a test. If these should change please let me know.

[AMerc.8]

When I set the logic analyzer to capture at 100M I get the following:

and when I set it to 50M I get the same plot as before:

[AScha.3]

...but always + only : when  clk AND mosi going low . so this is some ground bounce artifact or induced by capacitive or inductive coupling.

all port pins on low speed setting?

[waclawek.jan]

Sometimes it's inductive/capacitive coupling, but most of the time these are effects of improper prototyping techniques (flying leads, using breadboards) and inadequate ground/return.

> Right now I have the MOSI and SCK lines set to low for max output speed

What is that, in terms of GPIO_OSPEEDR values?

JW