STM32H7 MAC Software Reset Initialization Error
- September 5, 2026
- 4 replies
- 65 views
I have a custom board using STM32H735ZGT6 and the LAN8742 Ethernet PHY using RMII. During the execution of CubeMX generated Ethernet initialization code, the MAC software reset bit is not cleared triggering an error. I have read a lot of forum posts about this issue and have verified the following:
- The RMII reference clock is supplied by the PHY using a 25MHz crystal as in the H723 nucleo board. The 50MHz clock generated by the PHY is present at PA1 pin and verified with an oscilloscope. (see osci image below)
- VDDCR voltage is 1.2V generated by internal regulator on PHY
- The PHY hardware reset is supplied by a MCU GPIO, and the resistor straps seem to function properly during reset (probed all with oscilloscope). I also have a pulldown resistor on the LED2 pin so that REFCLKO is generated by PHY.
- I can communicate through MDIO with the PHY to read out and write to registers, confirming that straps work ok.
- The output side of the PHY works, a link is established in both 10 and 100Mbps mode.
- The standard CubeMX ethernet initialization is used meaning the MAC, TX, RX clocks are enabled, GPIOs are set to AF11 very high frequency mode, MAC RMII is enabled
- the clock settings and RMII enabled is verified by reading out the PMCR and AHB1ENR registers
Does anybody have an idea what the issue could be? The clock signal quality looks good enough to me but can somebody weigh in on it? I also have the MCU core clocked to 192MHz and VOS1 is used on the LDO, does the power and frequency setup have any bearing on the MAC? Should i be thinking about silicon GPIO damage at this stage?
I am attaching the oscilloscope image of the RMII clock (probed with a long ground lead and 10x probe, so the signal is probably worse than it actually is) as well as the PHY schematic.
ETH Init code
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
uint32_t tickstart;
if (heth == NULL)
{
return HAL_ERROR;
}
if (heth->gState == HAL_ETH_STATE_RESET)
{
heth->gState = HAL_ETH_STATE_BUSY;
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
ETH_InitCallbacksToDefault(heth);
if (heth->MspInitCallback == NULL)
{
heth->MspInitCallback = HAL_ETH_MspInit;
}
/* Init the low level hardware */
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
}
uint32_t abh1enr = RCC->AHB1ENR;
__HAL_RCC_SYSCFG_CLK_ENABLE();
HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
uint32_t pmcr = SYSCFG->PMCR;
/* Dummy read to sync with ETH */
(void)SYSCFG->PMCR;
/*
HAL_ETH_SetMDIOClockRange(heth);
//HAL_ETH_WritePHYRegister(heth, 0, 4, 0x01E1); advertise 100mbps full/half duplex, 10mbps full/half duplex
//HAL_ETH_WritePHYRegister(heth, 0, 27, 0x0000); autonegotiation enabled
HAL_ETH_WritePHYRegister(heth, 0, 0, 0x2100); //autonegotiation disabled, force 100mbps
//insert a code here that if the negotiation times out it reverts to 10mbps
uint32_t regValue;
HAL_ETH_ReadPHYRegister(heth, 0, 0, ®Value);
*/
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for software reset */
while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
{
if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
{
/* Set Error Code */
heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
/* Set State as Error */
heth->gState = HAL_ETH_STATE_ERROR;
/* Return Error */
return HAL_ERROR;
}
}HAL ETH MSP Init
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(heth->Instance==ETH)
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ETH1MAC_CLK_ENABLE();
__HAL_RCC_ETH1TX_CLK_ENABLE();
__HAL_RCC_ETH1RX_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**ETH GPIO Configuration
PC1 ------> ETH_MDC
PA1 ------> ETH_REF_CLK
PA2 ------> ETH_MDIO
PA7 ------> ETH_CRS_DV
PC4 ------> ETH_RXD0
PC5 ------> ETH_RXD1
PB11 ------> ETH_TX_EN
PB12 ------> ETH_TXD0
PB13 ------> ETH_TXD1
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN ETH_MspInit 1 */
/* USER CODE END ETH_MspInit 1 */
}
}
