stm32h7 lwip sdmmc1 fatfs

[GPHIL.1]

Hi,

Is there any sample for H755 with lwip eth and sdmmc1 fatfs?.

How configure the MPU region?.

 

Thanks,

 

 

 

 

[KDJEM.1]

Hello @GPHIL.1 ,

I advise you to configure your project step by step.

You can start by ethernet, for that I recommend you this FAQ: How to create project for STM32H7 with Ethernet and LwIP stack working. This article can help you to configure Cortex-M7.

Also, an STM32H745_Nucleo_M7_ETH example is available in STM32H7-LwIP-Examples.

Getting started with STM32H7 Series SDMMC host controller application note can help you to to read/write with SDMMC host interface using file system FATFS.

I hope this help you.

Kaouthar

[GPHIL.1]

Hi,

Thanks
I create a program with Lwip and fatfs managed by two thread
but to its'seems a conflict between fatfs and ETH and the dcache
if i initialize mpu config after enable D cache (SCB_EnableDCache)
i have a hardfault handler

see

void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};

/* Disables the MPU */
HAL_MPU_Disable();

/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0x0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

HAL_MPU_ConfigRegion(&MPU_InitStruct);

/** Initializes and configures the Region and the memory to be protected
* for LwIP RAM heap
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.BaseAddress = 0x30020000;
MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

HAL_MPU_ConfigRegion(&MPU_InitStruct);

/** Initializes and configures the Region and the memory to be protected
* for ETH DMA descriptors
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
MPU_InitStruct.BaseAddress = 0x30040000;
MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;

HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Configure the MPU attributes as Normal Non Cacheable for SRAM1 */
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x24000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Enables the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

}

main()...

/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();

/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();

/* MPU Configuration--------------------------------------------------------*/
MPU_Config(); -->hard fault handler

if i initialize mpu config between SCB_EnableICache and SCB_EnableDCache, it works

/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();

/* MPU Configuration--------------------------------------------------------*/
MPU_Config(); -->succeed

/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();

Have you any explainations?

Thanks

[KDJEM.1]

Hello @GPHIL.1 ,

This hard fault due to wrong sequence and the correct sequence is to configure MPU firstly, then enable cache.

It is recommend to configure MPU before enabling the caches. This is because the MPU settings can be affect the behavior of the caches. 

I think Level 1 cache on STM32F7 Series and STM32H7 Series application note can help to use cache.

Thank you.

Kaouthar