STM32H7 FMC SRAM Mode D write timing diagram

[Alex A]

I'm looking at the STM32H7 reference manual (RM0433 Rev 5) and the SRAM Mode D writing diagram seems to be incorrect:

The data bus should be driven by the MCU and NWE should go low, but the diagram shown is identical to the read diagram.

So what are the correct waveforms?

...and the manual should be updated with them.

[Khouloud GARSI]

Hi Alex,

The "Mode D read access waveform" figure is duplicated on the reference manual! Sorry for this inconvenience and thanks for bringing this to our attention.

We will add the correct waveforms to the next release of the RM.

Meanwhile, please find attached the correct "Mode D write access waveforms".

Khouloud.

[Khouloud GARSI]

Hi @Alex A​ ,

The RM is updated and the correct figure of "Mode D write access waveforms" is added.

Thanks again for your feedback!

Khouloud.