STM32H7 FMC SDSR busy bit is not documented or doesn't exist?

[berendi]

I've come across the following code in system_stm32h7xx.c, present in all example projects in STM32CubeH7

 FMC_Bank5_6_R->SDCMR = 0x00000009; 
 tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
 while((tmpreg != 0) && (timeout-- > 0))
 {
 tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
 }

Looks like it's waiting for some status bit to clear after issuing an SDRAM command.

This bit is however neither in the STM32H7 reference manuals (RM0399, RM0433) nor in the stm32h7*.h headers defined.

Reference manuals and headers for the STM32F4 series define this as a BUSY bit.

The STM32H7 reference manuals mention a "BUSY status flag" in the SDRAM controller / Low-power modes section, but there is no word on where to find it.

[ILutz.1]

I found your question when I was wondering about the same piece of CubeH7 code. Did you ever get some answer or other helpful information on this?

[Aleks]

Hi!

The same question for STM32H725 (RM0468). But in the reference for STM32F7 this bit is described:

Bit 5 BUSY: Busy status

This bit defines the status of the SDRAM controller after a Command Mode request

0: SDRAM Controller is ready to accept a new request

1; SDRAM Controller is not ready to accept a new request

It seems there are similar errors in some documents, but this bit is not precent in IDE

So so, where is comment from ST?