STM32H7 FMC data corruption

[JQiao.1]

FMC bank 1 is set to NOR Flash PSRAM, bank 3 is set to NAND Flash. The transfer of NAND flash uses DMA.

MPU of the above regions are set to non-cacheable, non-buffable, non-shareable.

The issue occurs when PSRAM read happens during NAND flash read. The DMA transfer result skipped bytes in the middle and are padded with PSRAM data in the end.

This should never happens as the manual specifies FMC "performs only one access at a time to an external device".

Did anyone see the same or similar issue?

Thanks.

[JQiao.1]

I have searched the web: several posts had similar issues and they could fix it by setting up MPU but it doesn't work for us.

We set 3 memory regions: external flash (16MB), external RAM (8MB), NAND flash (256MB).

If there is anything missing please let me know:

 //Region 0 - external flash 
 MPU->RNR = 0;
  
 //External flash base address
  MPU->RBAR = 0x60000000;
  
 //XN=Disabled, AP=Full Access, TEX=Level 2, S=Not Shareable, C=Not Cacheable, B=Not bufferable, SRB=Disabled, Size=16MB, Enable=1 
 MPU->RASR = (1 << MPU_RASR_XN_Pos) | 
 (3 << MPU_RASR_AP_Pos) | 
 (2 << MPU_RASR_TEX_Pos) | 
 (0 << MPU_RASR_S_Pos) | 
 (0 << MPU_RASR_C_Pos) | 
 (0 << MPU_RASR_B_Pos) | 
 (1 << MPU_RASR_SRD_Pos) | 
 (0x17 << MPU_RASR_SIZE_Pos) | 
 (1 << MPU_RASR_ENABLE_Pos);
  
 //Region 1 - external RAM 
 MPU->RNR = 1;
  
 //External Ram base address 
 MPU->RBAR = 0x64000000;
  
 //XN=Disabled, AP=Full Access, TEX=Level 2, S=Not Shareable, C=Not Cacheable, B=Not bufferable, SRB=Disabled, Size=8MB, Enable=1 
 MPU->RASR = (1 << MPU_RASR_XN_Pos) |
  (3 << MPU_RASR_AP_Pos) | 
 (2 << MPU_RASR_TEX_Pos) | 
 (0 << MPU_RASR_S_Pos) | 
 (0 << MPU_RASR_C_Pos) | 
 (0 << MPU_RASR_B_Pos) | 
 (1 << MPU_RASR_SRD_Pos) | 
 (0x16 << MPU_RASR_SIZE_Pos) | 
 (1 << MPU_RASR_ENABLE_Pos);
  
 //Region 2 - NAND flash 
 MPU->RNR = 2;  
 
 //NAND Flash start address 
 MPU->RBAR = 0x80000000 
  
 //XN=Disabled, AP=Full Access, TEX=Level 2, S=Not Shareable, C=Not Cacheable, B=Not bufferable, SRB=Disabled, Size=256MB/2gb, Enable=1 
 MPU->RASR = (1 << MPU_RASR_XN_Pos) | 
 (3 << MPU_RASR_AP_Pos) | 
 (2 << MPU_RASR_TEX_Pos) | 
 (0 << MPU_RASR_S_Pos) | 
 (0 << MPU_RASR_C_Pos) | 
 (0 << MPU_RASR_B_Pos) |
  (1 << MPU_RASR_SRD_Pos) | 
 (0x1B << MPU_RASR_SIZE_Pos) | 
 (1 << MPU_RASR_ENABLE_Pos);