STM32H7 APB and AHB peripheral clock limits

[Gpeti]

What are the upper limits on the APB and AHB peripheral clock on a STM32H743 ?

According to figure 46 of the reference manual:

the limit is 240MHz (or 200Mhz depending on the silicon revision I assume ?).

However STMicro HAL example set the APB and AHB peripheral frequency to 100MHz (SysClock on PLL at 400MHz, then D1CPRE=1, HPRE = 2 and for exemple D2PPRE1 = 2 for APB1).

Should I conclude that APB1 maximum clock is 100MHz ?

[Gpeti]

Sorry I've found another topic that answers my question: https://community.st.com/s/question/0D50X0000AU4sQJ/maximum-apb-clock-frequency-on-stm32h743-family

Figure 1 of the datasheet confirms APB and AHB maximum clocks but it is not written very clearly.

[berendi]

AHB limit is 240 MHz for revision V, 200 MHz for revision Y.

APB limit is 120 MHz for revision V, 100 MHz for revision Y.

For rev V, it is in Table 122 of the datasheet. It is omitted from the corresponding Table 24 for rev Y, but you can conclude it from the fact that the main difference is VOS 0 missing from rev Y.

The answer you have linked was written well before rev V has appeared.

> However STMicro HAL example set the APB and AHB peripheral frequency to 100MHz 

HAL functions and example projects are just that, examples. They are never meant as replacements for documentation.

By the way, there is an example in Projects/NUCLEO-H743ZI/Examples/PWR/PWR_VOS0_480MHZ. Guess what does it do.

[Gpeti]

I know HAL are not documentation !

I just missed the information in the ref manual + datasheet.