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GHARI.1
Associate III
October 9, 2021
Solved

STM32H7 ADC using timers

Hello,

I am using Nucleo-H743ZI ,I am using timer1 to trigger ADC.

My APB1 clock frequency is 240MHz and my ARR register is 240 of timer 1. So my sampling rate of ADC should be 1Msamples/sec. To check it I am toggling a pin whenever ADC conversion complete is done.

Instead of 1Msamples/sec I am getting around 250Ksamples/sec what might be the issue.

For low PWM frequency the relation (TIMER1_freq=APB1_frequency/ARR) is working fine as I decrease ARR my PWM output is not following above formulae.

Can anyone help me out what might be the issue?

This topic has been closed for replies.
TDK
TDKBest answer
October 9, 2021
Maybe I answered too quickly.
You would use the TRGO event to trigger the ADC. It’s unclear what “using timer 1�? to trigger the adc means. If you are triggering it within the interrupt, that is not going to work at 1 Msps. The TRGO event doesn’t using the cpu to trigger it.
Use DMA to send the result to memory directly without cpu intervention. Process data in a half or full transfer complete interrupt.
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13 replies

TDK
October 9, 2021

Your processor does not have infinite power. Trying to call an interrupt at 1 MHz is overloading the system and it can't keep up.

> TIMER1_freq=APB1_frequency/ARR

The equation, at least in how it relates to ARR, is actually:

> TIMER1_freq = APB1_frequency / (ARR + 1)

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GHARI.1
GHARI.1Author
Associate III
October 9, 2021

Then how should I trigger ADC to get 1 Mega samples/sec​

TDK
October 9, 2021
The same way you are now. Just don’t enable the interrupt.
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tolix
Associate
September 6, 2022

Hi! If you are getting 250K samples instead of 1M samples (4 times lesser), then the problem may be in the Length parameter in functions like HAL_ADCEx_MultiModeStart_DMA(...). The Length parameter should be not in bytes as declared in the description, but in number of transfers. So, if you use dual mode (1 word = 4 bytes per DMA transfer) and specify Length in bytes, you will get exactly 4 times lesser ADC rate, because DMA will stop after N * 4 number of transfers.