STM32H5E5 SPI slave: TX shift register width and Tx FIFO to Tx shift register transfer width
I'm using SPI1 on an STM32H5E5 in slave mode, with DSIZE = 32 bits, TSIZE=0 and `FTHLV` configured for four 32-bit frames.
I'm trying to understand the internal transmit pipeline more precisely.
Is the internal TX shift-register width (in bits) or transfer granularity documented anywhere for the STM32H5E5 please?
What is the effective width of the TX shift register, and how does data move from the byte-organised TX FIFO into it?
I would appreciate clarification of the internal TX FIFO to TX shift register data flow please?
For a 16 byte Tx FIFO, assume the TX FIFO is pre filled and full, as transmission begins, data transfers from the TX FIFO into the TX shift register so the Tx FIFO has new space immediately. So the TX FIFO becomes empty before the RX FIFO becomes full. What I'm trying to discover is how many SCLK pulses occur between TX FIFO empty and RX FIFO full. I expected it to be around 32 SCLK's (32 bit) but its closer to 8 SCLK's closer to one byte rather than one word.
Any information explaining this much appreciated.