STM32H563IIK6; Ok to let Vref floating?

[MarwinS]

Dear Community,

Chip: STM32H563IIK6
Package: UFBGA(176+25)

we are facing an issue where the VREF (+/-) Balls are wrongly connected in the design (VREF+ on GND and VREF- on Vcc). Means the design is not working. We tried a rework to connect the Vref+/- with very tiny wires but this is very complex and the result is most time not working.

Is there any chance to let both pins floating, means we do not connect VREF+ and VREF-? This rework we can do easily.

Thanks a lot
Marwin

[AScha.3]

Hi,

How many boards with this incorrect layout have been produced?

If just 5 boards or so, give them to recycling and make new test boards with correct connections.

If many boards...you can see it as a lesson to be learned: just make a few boards first, to test and verify a new design.

[MarwinS]

Hi AScha.3,
Thanks for reminding me.

Re-Design are already in production. Right now we have fixed timeplans, so I have give the rework a try.

Bye
Marwin

[AScha.3]

Hi,

sorry for reminding …

So just try it, with cut connection to VREF (+/-) ; as from ds vref has to be < 0.4V to vdda.

Obviously there are protection diodes connecting vdda to vref.

So leaving VREF (+/-) open, should be no drama, as long as you dont use any analog functions (ADC etc.)

As the the boards go to trash anyway, try it.

[mƎALLEm]

Hello,

Unfortunately not guaranteed. You can connect VREF+ to the ground instead of VDDA but you must connect VREF- to VSSA.

From the product datasheet:

 

[MarwinS]

Hello
mƎALLEm thank you very much for the clarification.
We have eased the rework with only to connect the Vref- to GND and let Vref+ floating.

Therefore we are able to proceed with the bringup until the changed designs arrive in some weeks.

Bye

Marwin