STM32H503RB I3C Target TX-FIFO Size Question

[BRIAN_LAI]

I am using NUCLEO-H503RB as I3C Target with LL library.
What's the minimum size of TX-FIFO available when I3C Target is reading by Controller?
I setup I3C Target TX-FIFO using function "LL_I3C_ConfigTxPreload" with 1 byte, but it always runs 8 bytes per time.

According to the datasheet, the size of TX-FIFO would be TGTTDCNT if size is lower than 8 bytes.
Tx-FIFO

My TGTTDCNT settings:
TGTTDCNT

The test procedure is I3C Controller start a private read with 11 bytes and Target return the array contents.
The source code is attached, the result diagram is described below.
I3C Read Test

[Foued_KH]

Hello @BRIAN_LAI , 

The minimum size of TX-FIFO available when I3C Target is reading by Controller is 1 byte.
You need to indicate the status of TX FIFO preload (target mode) by using : LL_I3C_IsActiveTxPreload. Then you can Set TX FIFO Preload (target mode) LL_I3C_ConfigTxPreload

Foued

[BRIAN_LAI]

Hi @Foued_KH ,

I think the root cause may be the Target Interrupt "I3C_EVR_TXFNFF" trigger when TX-FIFO is not full with 8 bytes.
Is it required to fill TX-FIFO full every time before I3C Target being read from Controller?
Are we able to implement I3C Target with using TX-FIFO only a single byte?

[Foued_KH]

Hello @BRIAN_LAI , 
Just configure Tx Fifo Threshold : 1 byte 

/** Configure FIFO**/
sFifoConfig.TxFifoThreshold =HAL_I3C_TXFIFO_THRESHOLD_1_4;

Foued

[BRIAN_LAI]

Hi @Foued_KH ,

I've already setup with "I3C_TXFIFO_THRESHOLD_1_4".

The interrupt condition is "One or more free space available in TX-FIFO". (1 byte empty then trigger Interrupt)
Is it possible to change the interrupt condition to "TX-FIFO empty" ? (only trigger Interrupt when 8 bytes empty)

[Foued_KH]

Are you sure that you are sharing the target code ?
because I see the process for the dynamic addressing in the target side