Skip to main content
hyuk.1
hyuk.1
Associate
April 4, 2023
Solved

stm32g474 can bus off recovery?

1. Terminal setting: classic can, silent mode, 250kbps, commercial vehicle, stm32g474

2. Symptom: There is no problem during the test, but sometimes a problem occurs with the vehicle, probably because of a can error. Symptoms not reproduced.

3. Inquiries:

-. Can our terminal affect the external can bus in silent mode?

-. How to perform recovery in firmware when can bus off occurs?

This topic has been closed for replies.
Jaroslav JANOS
Jaroslav JANOSBest answer
ST Employee
April 4, 2023

Hi @hyuk.1​ ,

in the silent mode (also bus monitoring mode) only recessive bits are sent to the CAN bus, so no, your terminal cannot affect the external bus.

Regarding the bus off state, your terminal should not be able to get to this state, as it is in the bus monitoring mode in which it cannot transmit any message (bus off occurs only when transmit error counter >= 255).

Anyway, the recovery sequence is described in the reference manual: "If the device goes Bus_Off, it sets CCCR.INIT of its own, stopping all bus activities. Once CCCR[INIT] has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation."

BR,

Jaroslav

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
View in thread

1 reply

Jaroslav JANOS
Jaroslav JANOSBest answer
ST Employee
April 4, 2023

Hi @hyuk.1​ ,

in the silent mode (also bus monitoring mode) only recessive bits are sent to the CAN bus, so no, your terminal cannot affect the external bus.

Regarding the bus off state, your terminal should not be able to get to this state, as it is in the bus monitoring mode in which it cannot transmit any message (bus off occurs only when transmit error counter >= 255).

Anyway, the recovery sequence is described in the reference manual: "If the device goes Bus_Off, it sets CCCR.INIT of its own, stopping all bus activities. Once CCCR[INIT] has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation."

BR,

Jaroslav

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
    Terms & ConditionsAccessibility statement