STM32G4 PLL documentation errors

[Terry Greeniaus]

Hi,

The documentation between the STM32G4 RM0440 Rev 3 and between the individual MCU specifications is inconsistent when it comes to the PLL limits. In the documentation for RCC_PLLCFGR we have the following two statements:

PLLN: "The software has to set correctly these bits to assure that the VCO output frequency is between 64 and 344 MHz."

PLLM: "The software has to set these bits correctly to ensure that the VCO input frequency ranges from 2.66 MHz to 8 MHz."

However, in DS12288 Rev 2 (data sheet for STM32G474xB xC and xE), under "5.3.9 PLL Characteristics", we have the following limits:

fVCO_OUT: 96 MHz to 344 MHz (Range 1) or 96 MHz to 128 MHz (Range 2)

fPLL_IN: 2.66 MHz to 16 MHz

Could we get clarification on what the correct limits are?

Thanks!

[Imen.D]

Hello @Terry Greeniaus​ ,

Thank you for highlighting this.

The correct values of "PLL Characteristics" are in the datasheets.

We will modify RM0440 and remove wrong statements (there should be no numeric values – just reference to datasheet).

Best Regards,

Imen