STM32G4 ADC clock frequency limitations

[galens]

Hi,

I would like to get some clarification on the maximum STM32G4 ADC clock frequency. In the STM32G473xB datasheet (DS12712 Rev 2), on page 138 it shows a max fADC of 60 MHz for Range 1, single ADC operation. What exactly is meant by "single ADC operation"? Does this mean that on the G473, which has 5 ADCs, I can only use one ADC at a time if the ADC clock is 60 MHz? Or is this perhaps a reference to single versus dual mode? From my perspective there are at least three possible interpretations of 'single' in this context: single versus multiple ADCs, single versus differential, and single mode versus dual mode. There is plenty of room for confusion here, hence the request for clarification.

thanks,

galen

[Igor Cesko]

The single ADC operation means that only one ADC is performing conversion at one time. I datasheet Rev. 2 are also parameters for multiple ADCs operations - if more ADCs are converting at the same time.

The lower ADC speed for multiple ADCs operation is given by stability of the reference voltage VREF+ (there are current peaks from VREF+ in each cycle of the successive approximation which must be attenuated within one approximation cycle - and more ADCs in parallel produce higher current peaks). Therefore is very important to perfectly design the VREF+ decoupling (ceramic capacitor as close as possible between VREF+ and VSSA pins - each millimeter has influence in term of parasitic inductance at such high frequencies ~60MHz).

Regards

Igor

[Singh.Harjit]

@Igor Cesko​ Thank you - this is probably one of the best explanations I've read on this site. I say best because it talks about what causes the issue. Only way to improve it would be to add information to the datasheet that enables one to analyze the design and make sure it is correct.

One of the problems ST has not addressed, in datasheets, is that different packages have different performance because of inductance, substrate / lead frame characteristics, etc.

In another life, I had to deal with a lot of microvolt signals. We ended up putting LDOs and DCAPs on chip, next to each analog block to eliminate the system level and on chip noise sources...

[Asantos]

This sounds like an errata that has become a specification.

The G4 ADC clock should be at least 75MHZ, to be clocked by the AHB bus and have the CPU and Timers clocks at 150MHZ. Standard configuration of the STM32cubeG4 examples.

ST should release an application note showing what is the ADC accuracy (ET, EO, EG,ENOB, etc) when clock is 75MHZ.

Is there plans to improve the G4 ADC clock frequency?

[waclawek.jan]

This issue IMO is as result of using some new, in a larger scale unproven silicon technology for the 'G4, resulting in unexpectedly large analog currents. One of the witnesses is also the extremely high supply current of comparators, which compared to 'F3 makes them unusable in current-sensitive appications (and makes the current-sparing method dealt with in the COMP appnote void). Other are the existing related ADC errata, "End of 10/8/6-bit ADC conversion disturbing other ADCs" and "ADC input channel switching disturbs ongoing conversions". Yet another,most probably related, is "STM32G4 robustness improvement" PCN.

This is a pity as the 'G4 were apparently supposed to replace (potentially surpass) the 'F3, positioned as analog-intensive chips.

AN5346 sort of speaks of this issue, but does not speak specifically of multiple ADC running at once (except of the clock value in the initial table). The explanation given here by Igor ought to be clearly spelled out in there, and the clock limitation for multiple conversions going on simultaneously or staggered, ought to be explicitly dealt with in a separate subchapter.

And, why the heck no, give there also a comparison to other STM32 families in this regard.

And, as the wording in DS mentioned in opening post is clearly confusing, that ought to be improved, too.

> [75MHz] Standard configuration of the STM32cubeG4 examples.

If it's so, that's clearly a problem, too.

@Vincent Onde​ , here you have some specific 'G4-documentation-related tips for improvement.

JW

[Igor Cesko]

To answer the various usage cases: if one ADC is sampling and the rest ADCs are converting, ... another cases. Important are the current peaks from VREF+ which are present during successive approximation only (during conversion) and its "filtering" by decoupling to have VREF+ stable at each end of ADC clock cycle (successive approximation cycle). Therefore is very important the VREF+ decoupling: parasitic components (inductances) are so small that the oscillations are in range of GHz (LC circuit). By improper decoupling (placing capacitor far from VREF+ / VSSA pins) we can increase the parasitic inductance (approximation for wire is ~10nH/cm). Selected device package influences this parasitic inductance - because there are bonding wires (LQFP package) - therefore is better to use UFBGA, UFQFPN or WLCSP packages (this is also mentioned in the AN5346). The internal on chip inductance is much smaller than external (bonding + pins + PCB). This is more physical problem than design problem.

We can discuss about improvements: decrease of currents by decreasing sampling capacitor - but this causes increase of noise ; usage of another analog oriented technology - but here is also digital design and price is important, .... etc. Design of STM32G4 is well designed from analog point of view and balanced with digital support for analog oriented applications. The ADC frequency limitation is given by integration of 5 ADCs which parallel operation limits the maximum ADC frequency because the noise from VREF+ oscillations is more than LSB. There is only push to application designers that for high frequency analog application there must be well designed the PCB.

Multiple ADCs operation case in STM32G4 is also explained in AN5346 (chapter 2.6 STM32G4 multiple ADCs and parallel operations).

The initial STM32G4 ADC errata were corrected in the last device revision - as stated in erratasheet.

There is not planned ADC speed improvements in STM32G4.

We will probably improve the wording in datasheet - because "single" ADC operation and ADC in "single" mode are similar words (but the meaning is totally different). Better is to use "one ADC operation" / "multiple ADCs operation" (because we have single conversion and also single-ended input).

From physical point of view about conversion speed for successive approximation ADCs: ADC frequency is 60MHz. One ADC clock cycle takes 1/60MHz = 16ns. This 16ns is one successive approximation step. Within this 16ns must be capacitors network reconfigured (change of analog switches between capacitors), the capacitors must be recharged (+ current from/to VREF+), we must wait that voltages on all capacitors will become stable within 0.5LSB (0.4mV for 12bit ADC), then this stable capacitors voltage is compared by analog comparator with fixed voltage level, comparator provides on its output (propagation delay of comparator) the digital result for given evaluated bit (in 12-bit resolution) which is then sampled. All within 16ns (and digital design around).

Regards

Igor

[waclawek.jan]

> Multiple ADCs operation case in STM32G4 is also explained in AN5346 (chapter 2.6 STM32G4 multiple ADCs and parallel operations).

Indeed. I've overlooked this.

Thanks for the detailed explanation, Igor.

A comparison to other STM32 families' ADCs would still be a nice touch to AN5346, though.. and of course, a set of concise Cube-less examples... ;)

Jan

@Igor Cesko​