STM32G0x1 RM0444 errors for the FDCAN peripheral
Hi,
I have another round of corrections for the DS13560 and RM0444 documents, i.e. the STM32G0B1RE datasheet and the STM32G0x1 reference manual.
On the datasheet page 35, chapter 3.26, the RAM reserved for the FDCAN module is specified as 1-Kbyte where it should be 0.8-Kbyte, or more precisely 848 bytes (figure 398 of the RM).
It is also false in the RM page 1200, just above chapter 36.3.1.
It is however correctly specified as 0.8-Kbyte in the chapter 36.1, page 1196 of the RM.
In the RM, for the FDCAN, regarding the bit timing (chapter 36.3.1, p. 1200), it has copy/paste errors:
- For the nominal bit time:
- BS1 is programmable between 1 and 256 bit quanta (not between 1 and 16)
- BS2 is programmable between 1 and 128 bit quanta (not between 1 and 8)
- For the data bit time:
- BS1 is programmable between 1 and 32 bit quanta (not mentionned at all)
- BS2 is programmable between 1 and 16 bit quanta (not mentionned at all)
- On page 1201, same typo for SJW, it should be between 1 and 128 for the nominal bit timing, resp. between 1 and 16 for the data bit timing.
Also, as it is an engineering document, please write numbers directly (i.e. 8 instead of eight).
It is more clear when glancing quickly over a paragraph.
On page 1233, for the FDCAN_NBTP register description (it may appear in other places as well)
Again, it is an engineering document.
A phrase like "The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one." is correct but convoluted, while the equation from p.1201 would make the document more clear and easier to understand.
Best regards.
@Antoine Odonne I tag you as you answered on my previous remark regarding the DS13560.
Edit: Added the SJW typo