STM32G0 pin incompatibility

[waclawek.jan]

Really???

JW

[Uwe Bonnes]

For a G0 design, you need to redesign power pins anyway. So probably the changed IO pins do not matter to much.

[waclawek.jan]

Fair point.

However, pin compatibility was traditionally maintained across the whole STM32 family, and where significant differences occured, the datasheet pointed that out.

Even in case of board redesign, minimal changes are always welcome.

I write this up to the "STM32 gotcha" list.

JW

[Uwe Bonnes]

A real pinmux would come handy, like on NRF5 chips.

[waclawek.jan]

It would be interesting to hear an educated estimate what would such pinmux cost, both in terms of silicon area/dollars, and in speed penalty.

JW

[Viktor POHORELY]

There is a clear benefit behind the decision, to decrease number of power pins needed to supply G0 MCU. Based on that, there are more GPIO's available for application and G0 becomes no longer pin to pin compatible. Thus, pinout optimization has been performed.

[Uwe Bonnes]

By the way, are there any numbers for the chip internal capacitance between VSS and VDD? The patents around the decoupling features indicate some substantial capacitance.