STM32G0 - Initial PWR register settings

[JuM]

Checked PWR settings at startup.

Find PWR->SR2 status value 0x00000300.

According manual this tells

• Regulator in Low Power mode (LPR)
• Flash memory in power down

Is this initiated by Keil/ST-Link debugger?

Or are there errors in reference manual of register PWR->SR2?

[JuM]

Seems that debugger cannot get read access on PWR registers.

Tried to set LPMS in PWR->CR1

  PWR->CR1 &= ~PWR_CR1_LPMS;

  PWR->CR1 |= (PWR_CR1_LPMS_2 );    // 1xx, shutdown

but that does not change watch values of PWR-CR1 from 0x00000208...

[JuM]

Sorry, sorry...

Forgot to enable clock for peripheral PWR:

  RCC->APBENR1 |= RCC_APBENR1_PWREN;        // Enable clock

[TDK]

RM says that register is only partially reset.

Bit 9 REGLPF: Low-power regulator flag

This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits

the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency.

This bit is cleared by hardware when the regulator is ready.

0: The regulator is ready in main mode (MR)

1: The regulator is in low-power mode (LPR)

Bit 8 REGLPS: Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on

reset or Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared,

the wakeup from Standby mode time may be increased.

0: The low-power regulator is not ready

1: The low-power regulator is ready

So you're in low power run mode. Is that expected? Is your frequency less than 2 MHz as required?

The MCU enters low-power modes by executing the WFI (wait for interrupt), or WFE (wait for event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M0+ system control register is set on return from ISR.