STM32G0 DMA and DMAMUX connections

[sholojda]

Hi

I'm trying to write simple code on STM32G030. I read PM and RM for this uC. I try to find where is written which DMA channel is connected to which DMAMUX. for example DMA has 5 DMA channels numbered from 1 to 5 and DMAMUX has request lines numbered from 0 to propalby 4. But there is no description that DMA channel 1 is assigned to numrer 0 of DMAMUX output reguest line? I do not know why STM did so. I thing it sholud be clearly written.

Next thing, If uC like STM32g0b0 has two DMA channels where i can find space address of each DMA? I realy can not find in none ST document.

[waclawek.jan]

Yes, both these things ought to be clearly documented, in the DMAMUX chapter (as DMA chapter points to DMAMUX chapter for the interconnections details) and also in the Interconnects chapter (it's in the name of that chapter, isn't it). This in fact is the problem of all STM32s with DMAMUX and single-port DMA (H7's BDMA, maybe the L4+? I did not check) and I believe we've discussed this in the past here already.

The upcoming release of the 'G0Bx is a good opportunity to review all existing 'G0 RMs in this regard, IMO.

@Imen DAHMEN​ , can this please be inserted into the queue? Thanks.

JW

[sholojda]

I have got RM0454 in front of me. ST pionts it as a RM for STM32g030 uC as a basic and only RM for this. I'm looking for a chapter or something like "Interconnects" and i can not fing something like this. Cam you please piont me the exact page, cause mybe i'm blind.

And am I right thinking that channel 1 of DMA corresponds to the request output line 0 of DMAMUX? And only such connection is valid, i mean that i can not set DMA channel 1 to work with DMAMUX request line 1?

And what about DMA address in peripheral space, where it is pointed?

Please point it to me, because i try as much as i can i do not see it

thanks

[waclawek.jan]

By "ought" I mean that that information is not there, but it should be there... :) Sorry for the confusion.

> And am I right thinking that channel 1 of DMA corresponds to the request output line 0 of DMAMUX?

AFAIK, yes.

> And only such connection is valid,

Yes, it's a hard link.

In the 'G0Bx, probably, DMAMUX lines 0..6 correspond to DMA1's Channel 1..7, and DMAMUX lines 7..11 correspond to DMA2's Channel 1..5.

> And what about DMA address in peripheral space, where it is pointed?

RM0454 Rev 5, Table 5. STM32G0x0 peripheral register boundary addresses, on page 48, 0x4002 0400 - 0x4002 07FF 1 KB DMA2 , 0x4002 0000 - 0x4002 03FF 1 KB DMA1

Is this what you are looking for?

JW