STM32F756NG - cannot write every other 128 bits of flash?
I have multiple prototypes using the STM32F756NGH6. Some (4/10) have an odd STM32 flash failure where I can erase flash and I can write flash, but only the first 128 bits of every 256 bits. The "upper" 128 bits of flash are all 1s and cannot be written.
Using OpenOCD with a J-Link Pro, this is what the first bit of flash looks like:
> mdw 0x200000 0x40
0x00200000: 20050000 00201129 00201f49 00201ef9 ffffffff ffffffff ffffffff ffffffff
0x00200020: 00000000 00000000 00000000 00204eb1 ffffffff ffffffff ffffffff ffffffff
0x00200040: 00201179 00201179 00201179 00201179 ffffffff ffffffff ffffffff ffffffff
0x00200060: 00201179 00201179 00201179 00201179 ffffffff ffffffff ffffffff ffffffff
0x00200080: 00201179 00201179 00201179 00201179 ffffffff ffffffff ffffffff ffffffff
0x002000a0: 00201179 00201179 00201179 00201179 ffffffff ffffffff ffffffff ffffffff
0x002000c0: 00201179 00201179 00201179 00201179 ffffffff ffffffff ffffffff ffffffff
0x002000e0: 00201179 00201179 00201179 00201179 ffffffff ffffffff ffffffff ffffffffThe lower four dwords are correct (this is just the vector table for the application which is why so many ISRs are pointing to 0x00201179), but the upper four dwords are all 0xffffffff. This pattern (unable to write to the upper 128 bits of every 256 bits) persists throughout the entire 1MB region.
Suspecting poor soldering, I reflow the STM32, taking the time to use a board heater to get the 6 layer board up to a reasonable temperature to ensure good solder. Most times this does not work, sometimes causing RDP level 1 (read protection) to become enabled. Other times it does nothing. I can usually undo the read protection which will allow me to try to write again, but the same failure occurs.
If I replace the STM32 with a new one then the problem may or may not be present.
I fear I am damaging these devices when soldering them, but I'd like to know if anyone has seen this issue before.
A few notes about the specific wiring of the STM32:
- All supplies are 3.3V, well-bypassed with 100nF 100V X5R capacitors (less than 50mV ripple on the 3.3V supply)
- Due to an Altium vault component error, I have mistakenly wired PDR_ON (ball E5) to GND and BYPASS_REG (ball L5) to 3.3V. I have corrected this by using a local 1.2V supply for the nearby FPGA on VCAP_1 and VCAP_2
- Also since BYPASS_REG is disabling the internal regulator, I have PA0 strapped to 3.3V as per 2.18.2 in the datasheet.
- I'm using a 12MHz CMOS oscillator for clock on PH0 (ball G1). There is no 32kHz oscillator.
- I'm using SWD for all debug and flash operations
Any suggestions or hints or tests you'd like me to run to try to correct this would be very much appreciated.
Thanks,
-A.
