STM32f746G_DISCO board sdram configuration quesiton

[JChen.24]

Hi,

In the STM32F746G_DISCO board, FMC_SDRAM example, how to decide these parameters? Which section does it specify from sdram MT48LC4M32B2B5 datasheet?

 SDRAM_Timing.LoadToActiveDelay   = 2;

 SDRAM_Timing.ExitSelfRefreshDelay = 6;

 SDRAM_Timing.SelfRefreshTime     = 4;

 SDRAM_Timing.RowCycleDelay       = 6;

 SDRAM_Timing.WriteRecoveryTime   = 2;

 SDRAM_Timing.RPDelay             = 2;

 SDRAM_Timing.RCDDelay            = 2;

 hsdram.Init.SDBank            = FMC_SDRAM_BANK1;

 hsdram.Init.ColumnBitsNumber  = FMC_SDRAM_COLUMN_BITS_NUM_8;

 hsdram.Init.RowBitsNumber     = FMC_SDRAM_ROW_BITS_NUM_12;

 hsdram.Init.MemoryDataWidth   = SDRAM_MEMORY_WIDTH;

 hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;

 hsdram.Init.CASLatency        = FMC_SDRAM_CAS_LATENCY_2;

 hsdram.Init.WriteProtection   = FMC_SDRAM_WRITE_PROTECTION_DISABLE;

 hsdram.Init.SDClockPeriod     = SDCLOCK_PERIOD;

 hsdram.Init.ReadBurst         = FMC_SDRAM_RBURST_ENABLE;

 hsdram.Init.ReadPipeDelay     = FMC_SDRAM_RPIPE_DELAY_0;

Thanks.

[Tesla DeLorean]

The timing parameters are in clock cycles for the FMC, need to convert into nanoseconds, and need to be within the specs in the datasheet

ie if it wants 35ns min, 30ns won't work, but 40ns would, if from a 100 MHz timing source (4 cycles).

CAS, RAS, rows, columns, banks, surely those are in the datasheet.

Memory width would depend on part and board. Couple of occasions ST has used 16-bit data bus, on 32-bit parts, due to cost/availability, and used half the SDRAM capacity.