STM32F746 slower then STM32F407???

Posted on June 20, 2018 at 13:46

As i had lack of speed while using stm32f407 disco, i ordered stmf746 nucleo-144. And What suprised me was that it is slower then stmf407, despite that stm32f07 168 max mhz, and stmf756 is up to 216Mhz. I configured my code with CUBEMX. Simple test: 

While(1)

{

HAL_GPIO_WritePin

(GPIOD, GPIO_PIN_12, GPIO_PIN_SET);

HAL_GPIO_WritePin

(GPIOD, GPIO_PIN_12, GPIO_PIN_RESET);

}

gives me 150ns pulses on STM32F746

when the same test gives me 100ns on STM32F407.

I used HSE 8mhz external resonator. Aclually clock config were the same for both mcu, except that 

STM32F746 has 216 mhz max when stmf407 168.

So why is that? STM32F746  should be more powerful. Also it was released later

#stm32f407 #stm32f746 #external-rc

[Tesla DeLorean]

Posted on June 20, 2018 at 14:32

>>

So why is that? STM32F746  should be more powerful. Also it was released later

Perhaps jamming a GPIO up and down, via write buffers, and slower buses is not a good measure of computational work?

Posted on June 20, 2018 at 15:00

the same thing with SPI

[waclawek.jan]

Posted on June 20, 2018 at 22:53

... and the twice-as-much MHz 'H7

https://community.st.com/0D50X00009XkWanSAF

... ;)

gives me 150ns pulses onSTM32F746

when the same test gives me 100ns onSTM32F4

There may be other things influencing this sort of 'speed' too, but first, try switching on compiler optimization.

JW

Posted on June 21, 2018 at 07:34

Im not sure what do you mean by ''

switching on compiler optimization''. Guess its not about CUBEmx clock optimization. 

But anyway this is my clock config for both mcu's:

F4:

F7:

[waclawek.jan]

Posted on June 21, 2018 at 16:41

Im not sure what do you mean by '

switching on compiler optimization'

Read the manual to your compiler/toolchain. Surely there is a mention of optimization.

JW

[STOne-32]

Posted on June 21, 2018 at 00:13

Hi,

Performance on an MCU is not just Pin I/O toggle limited by many factors:  AHB speed ( Frequency, latency of CPU core write and propagation to the physical I/O and then external bus load ).

in advanced MCUs like the Cortex-M cores, Peripheral usage : SPI, I/O, Timer should work in autonomous way like using DMA or builtIn FIFOs to let  CPU Cortex do important tasks (Real MIPS) and math computation , Algos. not like legacy old MCUs.

on STM32F7 we have Cortex-M7 core providing twice M4 MIPS (STM32F4) Thanks to pipeline and dual issue instruction set when running at same speed. Then particular care should be taken from where code is put like Cache activation etc. 

Have te a look on this app note :

http://www.st.com/content/ccc/resource/technical/document/application_note/0e/53/06/68/ef/2f/4a/cd/DM00169764.pdf/files/DM00169764.pdf/jcr:content/translations/en.DM00169764.pdf

 

Good lecture,

Ciao

STOne-32

Posted on June 21, 2018 at 07:39

Hi, well ,as you can see clock config images above, sysclock is on max freq, also my code doesnt do any other tasks besides toggling a pin with HAL struct