Question
STM32F746-Disco SDRAM problem
Hi,
I have problem with the test of SDRAM memory. I use STM32F746 Discovery kit where is MT48LC4M32B2 memory. SDRAM size is 128-Mbit SDRAM but only 64-Mbit is accessible on kit. So I try to test the entire 8MB SDRAM memory. Unfortunately, when the last bank is tested test failed. I don’t have idea why.
I use HSE with frequency 216 MHz. For memory configuration using STM32Cube_FW_F7_V1.11.0\Drivers\BSP\STM32746G-Discovery\stm32746g_discovery_sdram.c and I enable I-Cache and D-Cache:
Timing.LoadToActiveDelay = 2;
Timing.ExitSelfRefreshDelay = 7;
Timing.SelfRefreshTime = 4;
Timing.RowCycleDelay = 7;
Timing.WriteRecoveryTime = 2;
Timing.RPDelay = 2;
Timing.RCDDelay = 2;
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;My memory test code is this:
int main(void)
{
/* Enable the CPU Cache */
CPU_CACHE_Enable();
/* STM32F7xx HAL library initialization:
- Configure the Flash prefetch
- Systick timer is configured by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
- Set NVIC Group Priority to 4
- Low Level Initialization
*/
HAL_Init();
/* Configure the system clock to 216 MHz */
SystemClock_Config();
BSP_SDRAM_Init();
uint32_t sdramAddr;
uint32_t TEST_PATTERN = 0xAAAAAAAA;
uint32_t size = 2*1024*1024;
uint32_t mask = (size - 1) / 2;
uint32_t offs;
uint32_t bank = 4;
switch (bank)
{
case 1:
sdramAddr = 0xC0000000;
break;
case 2:
sdramAddr = 0xC0200000;
break;
case 3:
sdramAddr = 0xC0400000;
break;
case 4:
sdramAddr = 0xC0600000;
break;
default:
break;
}
uint32_t * addr = (uint32_t *)sdramAddr;
// write the default pattern at each of the power-of-two offsets
for (offs = 1; (offs & mask) != 0; offs <<= 1)
{
addr[offs] = TEST_PATTERN;
}
// check for address bits stuck high
addr[0] = ~TEST_PATTERN;
for (offs = 1; (offs & mask) != 0; offs <<= 1)
{
if (addr[offs] != TEST_PATTERN)
{ // error
while(1);
}
}
// check for address bits stuck low or shorted
addr[0] = TEST_PATTERN;
for (offs = 1; (offs & mask) != 0; offs <<= 1)
{
addr[offs] = ~TEST_PATTERN;
if (addr[0] != TEST_PATTERN)
{ // error
while(1);
}
for (offs = 1; (offs & mask) != 0; offs <<= 1)
{
if ((addr[offs] != TEST_PATTERN) && (offs != offs))
{ // error
while(1);
}
}
addr[offs] = TEST_PATTERN;
}
done = 1;
/* Infinite loop */
while (1)
{
}
}If I test the bank 4 test failed, the test is OK for the banks 1, 2 and 3. I do not know where it might be error. Please help…
Marketa
