STM32F745 FMC SDRAM Interface Theoretical Timining

[FGrie.1]

Hello,

I want to setup a STM32F745IEK6 together with an SDRAM from Micron Type MT48LC8M16A2P-6A.

I analyzed the theoretical signal Intergrity for the devices and I had to end because of my question:

The setup time of MT48L is required with min. 1,5 ns. The Hold time is min. 0,8 ns.

The hold time for the Signals e. g. CAS, RAS, WE is given with 0 ns, but for my understanding this value has to be greater than the 0,8 ns from the SDRAM.

I only had the chance if I am increasing the Time of Flight between transmitter and receiver. Or are the both parts not compatible together

Can somebody help for my understanding.

Thank you and best regards

[Amel NASRI]

Hi @FGrie.1​ ,

Referring to the datasheets of MT48LC8M16A2P-6A and STM32F745IEK6, it is important to check the figures showing the various waveforms and explaining how the timing parameters are exactly calculated.

We see for example that the hold time (tCMH) is starting with clock rising edge in the SDRAM datasheet. In the STM32F745 datasheet, th(SDCLKL_Nxx) is starting with falling edge of the clock.

To compare them properly, you need to consider the clock period.

-Amel