STM32F7 SPI flush rx fifo

[Barber.Mark]

..

[Barber.Mark]

how to flush the FIFO in the SPI RX buffer.

[John F.]

I used,

	//test the rx fifo level and flush any residual data
	while(LL_SPI_GetRxFIFOLevel(SPI2) != LL_SPI_RX_FIFO_EMPTY)
	{
		LL_SPI_ReceiveData8(SPI2);	//read to empty fifo
	}

The other "gotcha" I found was that after configuring for 8 bit transfers, you have to independently set the FRXTH bit in CR2 so that received data is flagged after a single byte is received.

	//SPI2 is on APB1 54 MHz : this configures for 8 bit byte transfers
	
 SPI_InitStructure.TransferDirection = LL_SPI_FULL_DUPLEX;
 SPI_InitStructure.Mode = LL_SPI_MODE_MASTER;
 SPI_InitStructure.DataWidth = LL_SPI_DATAWIDTH_8BIT;
 SPI_InitStructure.ClockPolarity = LL_SPI_POLARITY_HIGH;	//clock rests high
 SPI_InitStructure.ClockPhase = LL_SPI_PHASE_2EDGE;			//slave latch data on rising edge
 SPI_InitStructure.NSS = LL_SPI_NSS_SOFT;
 SPI_InitStructure.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV32 ;	//54MHz / 32 ~ 1.6875 MHz
 SPI_InitStructure.BitOrder = LL_SPI_MSB_FIRST;
 SPI_InitStructure.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
 SPI_InitStructure.CRCPoly = 7;
 LL_SPI_Init(SPI2, &SPI_InitStructure);
 
	//set CR2 bit FRXTH (so that RXNE is generated on reception of 8 bit)
	LL_SPI_SetRxFIFOThreshold(SPI2, LL_SPI_RX_FIFO_TH_QUARTER);

[David Littell]

I just do two quick 16-bit reads of the Data Register at a point I know nothing's being clocked in at the same time. The FIFO's only 32 bits deep and it does no harm to read it if it's already empty.