STM32F7 FMC Synchronous CLKDIV=3

[paulkinzer9]

Posted on October 10, 2017 at 17:24

I'm looking to use the FMC in Synchronous PSRAM 16-bit mode, and need to run CLKDIV of 3 (or 4).  The reference manual (RM0410) waveforms seem to show only a setting of CLKDIV=2.  In figure 50/51, CLK is shown toggling every rising HCLK edge.  How does it behave when CLKDIV=3?

For example, in figure 50, NADV is low for 2 HCLKs, or 1 CLK period, and AD[15:0] is valid for 2 HCLKS before, and 1 HCLK after NADV rising edge.  How does it behave when CLKDIV=3?

Thanks,

-Paul

#stm32f7 #fmc #clkdiv

[waclawek.jan]

Posted on October 10, 2017 at 18:05

The reference manual (RM0410) waveforms seem to show only a setting of CLKDIV=2. 

IMO they show setting of CLKDIV=1:

JW

[waclawek.jan]

Posted on October 10, 2017 at 19:37

This was on STM32F407 and not and 'F7, but I believe it will be similar.

JW

[paulkinzer9]

Posted on October 10, 2017 at 20:47

JW - Yes, I meant HSECLK/2 (CLKDIV=1).  Your waveforms are helpful, thanks. 

Do you know the NADV relationship in a CLKDIV=2 (HSECLK/3) scenario?  Figure 50 shows 3 HSECLK cycles from NADV falling edge to the start of DATLAT.

[waclawek.jan]

Posted on October 10, 2017 at 22:54

Sorry, no. I understand that the FMC chapter in RM is severely lacking in the details.

I'd recommend you to  take a Nucleo board, and 'dry' configure it for the required FMC mode and take the waveforms (I don't have a F7 Nucleo at hand, and the Discos are limited by the existing on-board circuitry - nor have I the time :-()

Other option is to contact ST through FAE or the web support form.

JW