STM32F42xx SPI errata handling with 70pF load

[stucmath]

Hello

I was studying the errata sheet for my uC (STM32F427ZI) and found this entry:

Corrupted last bit of data and/or CRC, received in Master mode with delayed SCK feedback

For the possible workarounds a table with the maximum allowable APB frequency is listed.

But my problem is, that on my SPI channel I have 70pF load. So now I don't know how to setup my SPI channel to avoid the corrupted last bit.

Does anybody have some informaton about this?

Kind regards

Mathias

[waclawek.jan]

Well, it's more-less an RC constant of the output transistor's full-open resistance and the load capacitance, which delays the SCK, so with OSPEEDR set on SCK to high you should restrain the respective APB to 90MHz/(70pF/30pF).

Or change the hardware design.

JW

[stucmath]

Thank your for your reply.

So you're saying, if I run the APB below 90MHz (which I do with 84Mhz) and set the OSPEEDR set on SCK to high I should be fine?

I would like to hear that with a clear statement from ST!?!

[waclawek.jan]

No. Actually I said that you should run APB below 90MHz/(70pF/30pF) = 38.6MHz.

> I would like to hear that with a clear statement from ST!!?!

Then contact ST directly. This is mostly a user-driven forum.

JW

[stucmath]

Oh sorry, somhow I missed the calculation :see_no_evil_monkey:

Thank you very much for your help.

I will ask ST directly about this problem.