STM32F429ZIT6 doesn't start without debugging session

[Benjamin Brammer]

Hey Guys,

I have designed a custom board with the STM32F429ZIT6 which I programm with the STLink debugger together with TrueStudio. So far everything seems to work except that when I don't use a debugging session I have to manually make a reset on NRST pin or otherwise the processor will not start it's normal program execution. I have to do this every time power get's cycled.

I have one 4,7uF cap for overall buffering and then 10nF and 100nF at each Vdd and an extra ferrite bead for the Vdda pin but with 1µF and 10nF as a decooupling. I did not implemnt a 100nF cap from NRST to ground for short ESD burst but I doubt that this is the cause for the problem since after the manual reset everything works fine.

Do I maybe need a reliable power cycling with an external power supervisor chip doing the manual reset, or did I do something comepletely wrong?

My controller runs with 3,3V.

best regards

Benjamin

[Tesla DeLorean]

Make sure BOOT0 is pulled low strongly.

Issue suggests BOOT0 floats, and looks relatively high as the supply ramps and the processor starts running.

Yes, having a proper POR circuit might help by clamping NRST low for 100's ms after the supply thresholds at 2.85V or some percent below nominal is preferable, but in this case might mask the issue.

[Benjamin Brammer]

I have implemented a 10k from BOOT0 as from the DISCOVERY schematics suggested. Would you recommend a 4,7k?

Ah and I have BOOT1 with 10k floating at the moment because with GND the debugging would not work..

[Uwe Bonnes]

The value of the BOOT0 pulldown does not matter, as long as the input bias current does not pull the pin high. However you really should try with 100n at NRST. Why did you omit it?

[Benjamin Brammer]

To my regret, I did not read this in AN4488 (Getting started with STM32F4xxxx MCU hardware development ). And didn't see at once that the 100nF are also implemented inside the DISCOVERY schematics. But I really would wonder if this should be the cause, since the 100nF are only for short EM or ESD burst to not trigger the NRST. At least for my understanding.. otherwise I would get some resets when I run my program after manually reseting the controller.

[Uwe Bonnes]

100nF and 50 kOhm internal Pullup give 5 ms time constant. When you power cycle, the input voltage will be much less "nervous" after this 5 ms period. Please, try the capacitor at NRST and report back!

[Benjamin Brammer]

Off course! You are right! I will check on that immediately and report back.

[S.Ma]

Correct, the reset signal is intended to start the mcu once its power suppy are high enough to operate properly. In debug mode, Reset is typically not monitored by ST-Link.

[Uwe Bonnes]

Do you have VCAP1/VCAP2 external capacitor ? Do option bits disable Brownout supervision?

[Benjamin Brammer]

VCAP1/2 are present as 2,2µF . But I haven't programmed the brownout. And it seems as it is deactivated initially...I will try to get this fixed.

[Benjamin Brammer]

OK I programmed the optional bytes via the ST-LINK Utility. It didn't change the problem. But for a reason I don't know today in the lab it seems to work without a manual NRST reset. Strange to my believes but that's how it is now. Anyhow I think I will implement a robust POR circuit.

So for now it may seem as if the 100nF on NRST did the job. But I will watch this..

[Benjamin Brammer]

mhh....I programmed the option bytes via the ST-Link Utility to VBOR3 so level 3 which should be enough with 2,9V . sadly it still doesn't work...is it possible that the processor enters a fault handler for some reason that is not triggered in debugg mode?