[STM32F429 Flexible Memory Controller (FMC)] Is the write operation blocking for the CPU? (NO BURST MODE)

[GRoas]

I couldn't find this info on the Reference Manual, maybe because it is trivial, in case I'm sorry. When the CPU performs a single STR within the FMC address space, is it blocked until the entire write cycle of the peripheral is complete, or it only writes in one of the FMC data registers and goes on with the following instructions?

There is no communication back from FMC to the core, so how is synchronism managed (also for the reads)?

[waclawek.jan]

RM0090 in the introduction to FMC mentions a 16-word deep write FIFO, so writes should not wait until completion, as long as this FIFO is not full.

> There is no communication back from FMC to the core

Why do you think so? There is the standard wait mechanism of the AHB bus, and certainly it is used by FMC, too.

JW